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PDF UM2661 Data sheet ( Hoja de datos )

Número de pieza UM2661
Descripción Enhanced Programmable Communications Interface
Fabricantes UMC 
Logotipo UMC Logotipo



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No Preview Available ! UM2661 Hoja de datos, Descripción, Manual

(l)UMC
UM2661
Enhanced Programmable
Communications Interface
Features
Synchronous Operation
• 5 to 8-b it characters pi us parity
• Single or double SYN operation
• I nternal or external character synchronization
• Transparent or non-transparent mode
• Transparent mode OLE stuffing (Tx) and detection
(Rx)
• Automatic SYN or DLE-SYN insertion
• SYN, OLE and DLE-SYN stripping
• Odd, even, or no parity
• Local or remote maintenance loop back mode
• Baud rate: dc to 1M bps (1 X clock)
Asynchronous Operation
• 5 to 8-bit characters plus parity
• 1, 1% or 2 stop bit transmitted
• Odd, even, or no parity
• Parity, overrun and framing error detection
• Line break detection and generation
• False start bit detection
• Automatic serial echo mode (echoplex)
• Local or remote maintenance loop back mode
• Baud rate: dc to 1M bps (1 X c~ock)
dc to 62.5K bps (16X clock)
- dc to 15.625K bps (64X clock)
Other Features
• Internal or external baud rate clock
• 3 baud rate sets (2661-1, -2, -3)
• 16 internal rates for each set
• Double buffered transmitter and receiver
• Dynamic character length switching·
• Full or half duplex operation
• TTL compatible inputs and outputs
• RxC and TxC pins are short circuit protected
• 3 open drain MaS outputs can be wire-O Red
• Single 5V power supply
• No system clock required
• 28-pin dual-in-line package
Pin Configuration
Block Diagram
D2
D3
RxD
GND
D4
D5
D6
D7
TxC/SYNC
A1
CE
AO
R/W
RxRDY
D1
DO
VCC
RxC/BKDET
DTR
RTS
DSR
RESET
BRCLK
TxD
TxEMT/DSCHG
CTS
DCD
TxRDY
DATA BUS
00-07
RESET
AO
Al
RNV
CE
ClK
TxC
RxC
OSR
OCO
CTS
RTS
OTR
TxEMT/OSCHG
SYN/OlE
CONTROL
SYNl
REGISTER
SYN2
REGISTER
OLE
REGISTER
TRANSMIT
DATA
HOLDING
REGISTER
TRANSMIT
SHIFT
REGISTER
TxROY
TxO
RECEIVE
SHIFT
REGISTER
RxROY
RxO
7-3

1 page




UM2661 pdf
RxC (lX)
RTS ---,~______________________________________________________________________________________________~______________________
CTS)
----~---------------------------
I II III
II I II
II III I
II II II
II IIII
II I I II
TxD
DATA 1
DATA 2
DATA 3 - [
SYN 1
DATA 4
DATA 5
c
In
CEU
U
WRITE DATA 1 WRITE DATA 2
TXEN..J
U
WRITE DATA 3
-- -- --- ---
U
WRITE DATA 4
U
WRITE DATA 5
--- --- -
-1_ _ _ _ _ _ __
uTxRDY ---u-l....J
......
..I.... TxEMT
U LJ
u
ASYNCHRONOUS MODE 7-BIT CHARACTER, NO PARITY, 1 STOP BIT
Igl5:
TxD
CE]
WRITE DATA 1
TxEN ........J
!!!!
DATAl
I~II
~
!! !I
DATA 2
U
WRITE DATA 2
U
WRITE DATA 3
III
!I!!
DATA 3
TxEN
TxRDY
L-J
TxEMT
MARK
i I, !!! I
DATA 4
II
~-------------
U
WRITE DATA 4
U
WRITE FOR LE BREAK CMD
n----------------------------------
Figure 2_ Transmitter Operation Timing Diagram
c:
!
...eft
eft

5 Page





UM2661 arduino
inputs. These registers are cleared by a RESET input
(SR6 and SR7 excepted).
Mode Register 1 (M R1 )
MRll and MR10 select the communication mode and baud
rate multiplier. Note: the multiplier in asynchronous
mode applies only if the external input option is selected
by M R24 and RM25.
MR13 and MR12 select Character length. Character
length does not include the parity bit, when selected, and
does not include the start and stop bits in asynchronous
operation.
MR14, when set, selects parity. A parity bit will be
transmitted with each character, and a parity check will be
performed on each character received.
M R15 selects either odd or even parity.
In the asynchronous mode MR16 and' MR17 select the
number of stop bits; 1, 15 or 2. If 1X baud rate is pro-
grammed 1.5 stop bits defaults to 1 on transmit.
In the synchronous mode MR17 controls the number of
SYN characters used to establish synchronization, and
the number of fill characters to be transmitted when
TxRDY and TxEMT are O.
M R16 controls selection of the transparent mode. When
MR16 is set (transparent selected) DLE-SYNl is used for
character fill and SYN detect (SR 5), but the normal
synchronization sequence is used to establish character
UM2661
sync. When transmitting in the synchronous transparent
mode, a DLE character in the TxH R will cause a second
DLE character to be transmitted.. Note: if the send DLE
command (CR3) is active when a DLE character' is in the
TxHR only one additional DLE will be transmitted.
The bits in the mode register affecting character assembly
and disassembly (MR12-MR16) can be changed dynami-
cally (during active receive/transmit operation). The
character mode register affects both the transmitter and
receiver; therefore in synchronous mode, changes should
be made only in half duplex mode (RxEN=l or TxEN=l,
but not both simultaneously=l). In asynchronous mode,
character changes should be made when Rx EN and
TxEN=O or when TxEN=l and the transmitter is marking
in half duplex mode (RxEN =0).
To effect assembly/disassembly of the next received/
transmitted character, MR12--15 must be changed within
n bit times of the active going state of RxDRY/TxRDY.
Transparent and non-transparent mode changes (M R16)
must occur within n-l bit times of the character to be
affected when the receiver or transmitter is active.
(n = smaller of the' new and old character lengths.)
Mode Register 2 (MR2)
MR20 through M R23 select the internal Baud Rate
Generator (BRG). There are sixteen selectable rates for
each version as outlined in Table 1.
MR24 through MR27 define the receive and transmit
clock source and the function of pins 9 and 25. Reference
Figure 3.
Table 3. UM2661 Register Addressing
CE Ai ~
1 XX
000
000
001
001
0 10
0 10
0 11
0 11
RIW
X
0
1
0
1
0
1
0
1
,.
Functions
Three-state Data Bus
Read Receive Holding Register (RxHR)
Write Transmit Holding Register (TxHR)
Read Status' Register (SR)
Write SYN1/SYN2/DLE Registers
Read Mode Registers (MR1, MRl IMR2)
Write Mode Registers (MRl , MRl 1M R2)
Read Command Register
Write Command Register
7-13

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