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PDF UM8329 Data sheet ( Hoja de datos )

Número de pieza UM8329
Descripción Floppy Disk Interface Circuit
Fabricantes UMC 
Logotipo UMC Logotipo



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No Preview Available ! UM8329 Hoja de datos, Descripción, Manual

SUMO
UM832918329T18329BI8329BT
Features
• Digital date separator
Performs complete data separation function for
floppy disk drives
Separates FM and MFM encoded data
No critical adjustments necessary
5%" and 8" compatible
• Variable write precompensation
• Internal crystal osci lIator circu it
• Track-selectable write precompensation
• Retriggerable head-load timer
• Compatible with the FDC 179X, 8272A, and other
standard floppy disk controllers
• SAN-III MOS N-CHANNEL TECHNOLOGY
• Single + 5 volt supply
• TTL compatible
General Description
The UM8329/B is an MOS integrated circuit designed to
complement either the 179X or 8272A (765A) type of
floppy disk controller chip. It incorporates a digital data
separator, write precompensation logic, and a head-load
timer in one O.3-inch wide 20-pin package. A single pin will
/ configure the chip to work with either the 179X or 8272A
type of controller. The UM8329/B provides a number of
different dynamically selected precompensation values so
that different values may be used when writing to the
inner and outer tracks of the floppy disk drive. The
UM8329/B operates from a +5V supply and simply requires
that a 16 or 8 MHz crystal or TT L-Ievel clock be connected
to the XTAL/CLKIN pin. All inputs and outputs are TTL
compatible.
The UM8329 is available in four versions: The UM8329/T
are intended for 5%" disks and the UM8329B/T for 5%"
and 8" disks. The UM8329/B have an internal crystal
oscillator circuit; the UM8329TIBT require an external
clock.
Pin Configuration
Block Diagram
DSKD
FDCSEl
MINI
DENS
SEPClK
SEPD
WDOUT
HlT/ClK
ClKOUT
GND
VCC
P2
Pl
PO
TEST
HlD
lATE
EARLY
WDIN
XTAl/
ClKIN
6-34

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UM8329 pdf
OperationaL Description
UM8329/8329T183298/83298 T
INTCLK
SEPCLK ---.J
SEPD*----------~L-J
I
:
:I
~
alw'ays two internal clock cycles
LJ
LJ
*polarity of SEPD shown for FDCSEL= low.
DATA SEPARATOR
The XTAL/CLKIN input clock is internally divided by the
UM8329/B to provide an internal clock. The division ratio
is selected by the FDCSEL, MINI and DENS inputs depend-
ing on the type of drive used. (See fig. 1.)
The UM8329/B detects the leading (negative) edges of the
disk data pulses and adjusts the phase of the internal clock
to provide the SE PC LK output.
Separate short- and long-term timing correctors assure ac-
curate clock separation.
The SEPCLK frequency is nominally 1/16 the internal clock
frequency. Depending on the internal timing correction,
the duration of any SEPCLK half-cycle may vary from a
nominal of 8 to a minimum of 6 and a maximum of 11
internal.clock cycles.
FDCSEL
'0
0
0
0
1
1
1
1
Inputs
DENS MINI
0 O'
01
10
11
00
01
10
11
Fig. 1.
f(XTAL/CLKIN)
/f(lNTCLK)
2
4
4
8
4
8
2
4
PRECOMPENSATION
The desired precompensation delay is determined by the
state of the PO, P1 and P2 inputs of the UM8329/B as per
fig. 2. Logic levels present on these pins may be changed
dynamically as long as the inputs are stable during the time
the floppy disk controller is writing to the driver and the
inputs meet the minimum setup time with respect to the
write data from the floppy disk controller.
MINI P2 Pl PO Precomp Value
0 000
o ns
0 001
62.5 ns
0 0 10
125 ns
0 0 11
187.5 ns
0 100
250 ns
0 10 1
250 ns
0 110
312.5 ns
0 111
312.5 ns
1 000
o ns
1
00
1
125 ns
1 0 10
250 ns
1 0 11
375 ns.
1 100
500 ns
1 101
500 ns
1 110
625 ns
1 111
625 ns
Note: All values shown are obtained with a 16 MHz re-
ference clock. Multiply pre-comp values by two
for 8 MHz operation.
Fig. 2 Write precompensation value selection
HEAD LOAD TIMER
The head load time delay is either 40 msor 80 ms, depend-
ing on the state of MINI. (See fig. 3.) The purpose of this
delay is,to ensure that the head has enough time to engage
properly. The head load timer is only used in the 179X
mode; it is non-functional in the 8272A mode.
The FDC 179X initiates the loading of the floppy disk drive
head by setting H LD high. The controller then waits the
programmed amount of time until the H LT signal from the
goes high' before starting a read or write operation
UM8329/B.
Inputs
FDCSEL DENS
00
00
01
01
10
10
11
11
MINI
0
1
0
1
0
1
0
1
Outputs
CLKOUT HLT/CLK
2 MHz
1 MHz
2 MHz
1 MHz
40 ms*
80 ms*
40 ms*
80 ms*
500 KHz
250 KHz
1 MHz
500 KHz
8 MHz
4 MHz
8 MHz
4 MHz
Note:
All values shown are obtained with a 16 MHz
reference clock. Divide all frequencies and mUltip-
ly all periods by two for 8 MHz operation.
*May be mask programmed at factory to any value from 1
to 512 min is 15.625 jJ.S increments (MINI low) or 1 to
1024 nis in 31.25 jJ.S increments (MINI high).
Fig. 3. Clock and head load time delay selection
Inputs
FDCSEL DENS MINI
Floppy
Disk
Drive
Type
Floppy
Disk
Drive
Density
Floppy
Disk
Controller
Type
0 0 0 8" Drive Double 179X
0 0 1 5%" Drive Double 179X
0
1 0 8" Drive Single
179X
0
1 1 5%" Drive Single
179X
1 0 0 8" Drive Single 8272A (765A)
1 0 1 5%" Drive Single 8272A (765A)
1 1 0 8" Drive Double 8272A (765A)
1 1 1 5%" Drive Double 8272A (765A)
Fig. 4 Floppy disk. drive and controller selection
6-38

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