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PDF UM8272A-4 Data sheet ( Hoja de datos )

Número de pieza UM8272A-4
Descripción Floppy Disk Controller
Fabricantes UMC 
Logotipo UMC Logotipo



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No Preview Available ! UM8272A-4 Hoja de datos, Descripción, Manual

(l)UMC
UM8272A / UM8272A'-4
: : : : : : : : : : : : : Floppy Disk Controller
Features
• IBM Compatible in Both Single and Double Density
Recording Formats
• Programmable Data Record Lengths: 128, 256, 512,
or 1024 Bytes/Sector
• Multi-Sector and Multi-Track Transfer Capability
• Drives Up to 4 Floppy or Mini-Floppy Disks
• Data Transfers in DMA or Non-DMA Mode
• Parallel Seek Operations on Up to Four Drives
• Compatible with all intel and Most Other Mlcropro-
cessors
• SIngle-Phase 8MHz/4MHz Clock for UM8272A/
UM8272A-4 respectively
• Single + 5 Volt Power Supply 1COAl)
General Description
The UM8272A is an LSI Floppy DIsk Controller (FDC)
Chip, which contains the circuitry and control functions
for interfacing a processor to 4 Floppy Disk Drives, It is
capable of supporting either IBM 3740 single density
format (F rvi), or IBM System 34 Double Density fo rmat
(MFM) including double sided recording, The UM8272A
Pin Configuration
Block Diagram
RESET
RD
WR
CS
AO
DBo
DBl
DB2
DB3
DB4
DBs
DB6
DB7
DRO
DACK
TC
IDX
INT
ClK
GND
VCC
RW/SEEK
lCT/DIR
FR/STP
HDl
RDY
WP/TS
FlT/TRo
PS o
PSl
WDA
USo
USl
HD
MFM
WE
veo
RD
RDW
WCK
DBO-7
TERMINAL
. COUNT
ORO
DACK
INT
AD
WR
AO
RESET
cs ___-'
READY
WRITE PROTECT/TWO SIDE
INDEK
FAULT/TRACK 0
UNIT SELECT 0
UN IT SE LECT 1
MFM MODE
RW/SEEK
HEAD LOAD
HEAD SELECT
LOW CURRENT/DIRECTION
FAULT RESET/STEP
6-3

1 page




UM8272A-4 pdf
Pin Description
UM8272A /UM8272A.4
1\10.
1
2
3
4
5
6-13
14
15
16
17
18
19 .
20
21
22
Pin
Symbol
RST
Name
Reset
RD Read
WR Write
CS
Ao
DBo-DB7
DRO
DACK
TC
Chip Select
Data/Status Reg
Select
Data Bus
Data DMA
Request
DMA
Acknowledge
Terminal Count
IDX
INT
ClK
GND
WCK
Index
Interrupt
Clock
Ground
Write Clock
ROW
Read Data
Window
Input/
Output
Input
Connection
to
Processor
InputCD
Processor
InputCD
Processor
Input
InputQ)
CDInput
Output
Output
Input
Processor
Processor
Processor
DMA
DMA
Input
DMA
Input
Output
Input
FDO
ProcessQr
Input
Input
Phase lock loop
Functions
Places FDC in idle state Resets
output lines to FDD to "0" (low).
Does not eHect SRT, HUT or H l T
in Specify command. If RDY pin is
held high during Reset, FDC will
generate interrupt 1.024 ms later.
To clear th is interrupt use Sense
Interrupt Status command.
Contro I signal Tor transfer of data
from FDC to Data Bus, when "0"
(low).
Control signal for transfer of data
to FDC via Data Bus, when "0"
(low).
IC selected when "0" (low), allow-
ing RD and WR to be enabled.
Selects Data Reg (Ao = 1) or Status
Reg (Ao = 0) contents of the FDC
to be sent to Data Bus.
Bi-Directional 8-Bit Data Bus.
DMA Request is being made by
FDC when DRW = "1"
DMA cycle is active when "0"
(low) and Controller is performing
DMA transfer.
Indicates the termination of a DMA
transfer when "1" (high). It ter-
minates data transfer during Read/
Write/Scan command in OMA or
interrupt mode.
Indicates the beginning of a disk
track.
Interrupt Request Generated by
FDC.
Single Phase 8 MHz Squarewave
Clock.
D.C. Power Return.
Write Data rate to FDD. FM = 500
kHz, MFM = 1 MHz, with a pulse
width of 250 ns for both FM and
MFM.
Generated by Pll, and used to
sample data from FDO.
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UM8272A-4 arduino
UM8272A /UM8272A.4
Table 3. UM8272A Command Set (Continued)
PHASE
Command
Execution
Aesult
Command
Execution
Aesult
DATABUS
RIW 07 06 05 04 0 3 02 01 Do
REMARKS
, , ,SCAN LOW OR EQUAL
W MT MF SK
00
Command Codes
W X X X X X HD US, usa
w C Sector 10 information
W H prior Command
W A execution.
WN
W EOT
W GPL
W STP
Data·coMpared be·
tween the FDD
and main-system
A
STO
Status information
A
ST 1
after Command
A
ST2
execution
A C Sector 10 information
A H after Command
A A execution
AN
, , ,SCAN HIGH OR eQUAL
W MT MF SK 1 0
Command Codes
W X X X X X HD USl usa
W C Sector ID information
W H prior Command
W. A execution
wN
W EOT
W GPL
W STP
Data-compared be-
tween the FDD
and main-system
A
STO
Status information
A
ST 1
after Command
A
ST2
execution
A C Sector 10 information
A H after Command
A A execution
RN
PHASE
Command
Execution
Command
Aesult
Command
Command
Aesult
Command
Execution
Command
Aesult
DATABUS
RIW 07 06 05 04 03 02 0 1 Do
RECALIBRATE
REMARKS
W 0 0 0 0 0 1 1 1 Command Codes
W X X X X X 0 US, usa
Head retracted to
Track 0
,SENSE INTERRUPT STATUS
W 0000
0 0 0 Command Codes
A
STO
Status information at
A
PCN
the end of seck-opera-
tion about the FDC
, ,SPECIFY
W 000000
Command Codes
W -SAT
W HLT
..HUT-
NO
,SENSE DRIVE STATUS
W 00000
0 0 Command Codes
w X X X X X HD USl usa
A
ST 3
Status information
about FDD
, ,SEEK
W 0000
1
1 Command Codes
W X X X X X HD USl usa
W NCN
Head is positioned
over proper Cylinder
on Diskette
INVALID
W ----Invalid Codes - - - Invalid Command
Codes (NoOp - FDC
goes into Standby
State)
A
STO
ST 0 = 80
(16)
Polling Feature of the UM8272A
_..After power-up RESET, the Drive Select Lines DSO and
DS1 will automatically go into a polling mode. In be-
tween commands (and between step pulses in the SEE K
command) the UM8272A polls all four FDDs looking for
a change in the Ready line from any of the drives. If the
Ready line changes state (usually due to a door opening or
closing) then the UM8272A will generate an interrupt.
When Status Register 0 (STO) is read (after Sense Interrupt
Status is issued), Not Ready (NR) will be indicated: The
polling of the Ready line by the UM8272A occurs con-
tinuously between instructions, thus notifying the pro-
cessor which drives are on or off line. Approximate scan
timing is shown in Table 4.
Table 4. Scan Timing
OS1 OSO APPROXIMATE SCAN TIMING
00
220fJ.S
01
220fJ.S
10
220fJ.S
11
440fJ.S
Command Descriptions
During the Command Phase, the Main Status Register must
be polled by the CPU before each byte is written into the
Data Register. The DIO (DB6) and ROM (DB7) bits in
the Main Status Register must be in the "0" and "1" states
respectively, before each byte of the command may be
written into the UM8272A. The beginning of the ex-
ecution phase for any of these commands will cause DIO
and ROM to switch to "1" and "0" states respectively.
READ DATA
A set of nine (9) byte words are required to place the FDC
into the Read Data Mode. After the Read Data command
has been issued the FDC loads the head (if it is in the
unloaded state), waits the specified head setting time
(defined in the Specify Command), and begins reading ID
address Marks and ID fields. When the current sector
number ("R") stored in the ID Register (IDR) compares
with the sector number read off the diskette, then the FDC
outputs data (from the Data field) byte-by-byte to the main
system via the data bus.
After completion of the read operation from the current
sector, the Sector Number is incremented by one, and
the data from the next sector is read and output on the
data bus. This continuous read function is called a "Multi-
Sector Read Operation." The Read Data Command must
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