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PDF CD4050BC Data sheet ( Hoja de datos )

Número de pieza CD4050BC
Descripción Hex Non-Inverting Buffer
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! CD4050BC Hoja de datos, Descripción, Manual

October 1987
Revised January 1999
CD4049UBC • CD4050BC
Hex Inverting Buffer •
Hex Non-Inverting Buffer
General Description
The CD4049UBC and CD4050BC hex buffers are mono-
lithic complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode
transistors. These devices feature logic level conversion
using only one supply voltage (VDD). The input signal high
level (VIH) can exceed the VDD supply voltage when these
devices are used for logic level conversions. These
devices are intended for use as hex buffers, CMOS to DTL/
TTL converters, or as CMOS current drivers, and at VDD =
5.0V, they can drive directly two DTL/TTL loads over the
full operating temperature range.
Features
s Wide supply voltage range: 3.0V to 15V
s Direct drive to 2 TTL loads at 5.0V over full temperature
range
s High source and sink current capability
s Special input protection permits input voltages greater
than VDD
Applications
• CMOS hex inverter/buffer
• CMOS to DTL/TTL hex converter
• CMOS current “sink” or “source” driver
• CMOS HIGH-to-LOW logic level converter
Ordering Code:
Order Number Package Number
Package Description
CD4049UBCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4049UBCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD4050BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4050BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP
CD4049UBC
CD4050BC
Top View
© 1999 Fairchild Semiconductor Corporation DS005971.prf
Top View
www.fairchildsemi.com

1 page




CD4050BC pdf
Switching Time Waveforms
Typical Applications
CMOS to TLL or CMOS at a Lower VDD
VDD1 VDD2
In the case of the CD4049UBC the output drive capability increases with increasing input voltage.
E.g., If VDD1 = 10V the CD4049UBC could drive 4 TTL loads.
5 www.fairchildsemi.com

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