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PDF IDT82V2081 Data sheet ( Hoja de datos )
| Número de pieza | IDT82V2081 | |
| Descripción | SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT | |
| Fabricantes | IDT | |
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SINGLE CHANNEL T1/E1/J1 LONG HAUL/
SHORT HAUL LINE INTERFACE UNIT
IDT82V2081
FEATURES:
• Single channel T1/E1/J1 long haul/short haul line interfaces
• Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
• Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024
- High impedance setting for line drivers
KHz - PRBS (Pseudo Random Bit Sequence) generation and detection
• Programmable T1/E1/J1 switchability allowing one bill of ma-
with 215-1 PRBS polynomials for E1
terial for any line condition
- QRSS (Quasi Random Sequence Signals) generation and detection
•
•
•
Single 3.3 V power supply with 5 V tolerance on digital interfaces
Meets or exceeds specifications in
- ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703,G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR12/13
- AT&T Pub 62411
Software programmable or hardware selectable on:
- Wave-shapingtemplatesforshorthaulandlonghaulLBO(LineBuild
Out)
- Line terminating impedance (T1:100 Ω, J1:110 Ω, E1:75 Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- B8ZS/HDB3/AMI line encoding/decoding
•
•
•
•
•
•
with 220-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
Cable attenuation indication
Adaptive receive sensitivity
Short circuit protection and internal protection diode for line driv-
ers
LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection
Supports serial control interface, Motorola and Intel Multiplexed
interfaces and hardware control mode
Package:
IDT82V2081: 44-pin TQFP
DESCRIPTION:
The IDT82V2081 can be configured as a single channel T1, E1 or J1 Line
Interface Unit. In receive path, an Adaptive Equalizer is integrated to
removethedistortionintroducedbythecable attenuation.TheIDT82V2081
also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and
detects and reports the LOS conditions. In transmit path, there is an AMI/
B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter
Attenuator, which can be placed in either the receive path or the transmit
path. The Jitter Attenuator can also be disabled. The IDT82V2081 supports
both Single Rail and Dual Rail system interfaces. To facilitate the network
maintenance, a PRBS/QRSS generation/detection circuit is integrated in
the chip, and different types of loopbacks can be set according to the appli-
cations. Four different kinds of line terminating impedance, 75 Ω, 100 Ω,
110 Ω and 120 Ω are selectable. The chip also provides driver short-circuit
protectionandinternalprotectiondiode. Thechipcanbecontrolledbyeither
software or hardware.
The IDT82V2081 can be used in LAN, WAN, Routers, Wireless Base
Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,
CSU/DSU equipment, etc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
2003 Integrated Device Technology, Inc. All rights reserved.
1
July 2004
DSC-6228/4
1 page  
SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
LIST OF TABLES
INDUSTRIAL
TEMPERATURE RANGES
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
Table-18
Table-19
Table-20
Table-21
Table-22
Table-23
Table-24
Table-25
Table-26
Table-27
Table-28
Table-29
Table-30
Table-31
Table-32
Table-33
Table-34
Table-35
Table-36
Table-37
Table-38
Table-39
Table-40
Table-41
Table-42
Table-43
Table-44
Table-45
Table-46
Pin Description ................................................................................................................ 9
Transmit Waveform Value For E1 75 Ω ........................................................................ 17
Transmit Waveform Value For E1 120 Ω ...................................................................... 17
Transmit Waveform Value For T1 0~133 ft................................................................... 17
Transmit Waveform Value For T1 133~266 ft............................................................... 18
Transmit Waveform Value For T1 266~399 ft............................................................... 18
Transmit Waveform Value For T1 399~533 ft............................................................... 18
Transmit Waveform Value For T1 533~655 ft............................................................... 18
Transmit Waveform Value For J1 0~655 ft ................................................................... 19
Transmit Waveform Value For DS1 0 dB LBO.............................................................. 19
Transmit Waveform Value For DS1 -7.5 dB LBO ......................................................... 19
Transmit Waveform Value For DS1 -15.0 dB LBO ....................................................... 19
Transmit Waveform Value For DS1 -22.5 dB LBO ....................................................... 20
Impedance Matching for Transmitter ............................................................................ 20
Impedance Matching for Receiver ................................................................................ 21
Criteria of Starting Speed Adjustment........................................................................... 23
LOS Declare and Clear Criteria for Short Haul Mode ................................................... 24
LOS Declare and Clear Criteria for Long Haul Mode.................................................... 25
AIS Condition ................................................................................................................ 25
Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 26
EXZ Definition ............................................................................................................... 29
Interrupt Event............................................................................................................... 33
Register List and Map ................................................................................................... 34
ID: Device Revision Register ........................................................................................ 35
RST: Reset Register ..................................................................................................... 35
GCF: Global Configuration Register ............................................................................. 35
TERM: Transmit and Receive Termination Configuration Register .............................. 35
JACF: Jitter Attenuation Configuration Register ........................................................... 36
TCF0: Transmitter Configuration Register 0 ................................................................. 36
TCF1: Transmitter Configuration Register 1 ................................................................. 37
TCF2: Transmitter Configuration Register 2 ................................................................. 37
TCF3: Transmitter Configuration Register 3 ................................................................. 38
TCF4: Transmitter Configuration Register 4 ................................................................. 38
RCF0: Receiver Configuration Register 0..................................................................... 38
RCF1: Receiver Configuration Register 1..................................................................... 39
RCF2: Receiver Configuration Register 2..................................................................... 40
MAINT0: Maintenance Function Control Register 0...................................................... 40
MAINT1: Maintenance Function Control Register 1...................................................... 41
MAINT2: Maintenance Function Control Register 2...................................................... 41
MAINT3: Maintenance Function Control Register 3...................................................... 41
MAINT4: Maintenance Function Control Register 4...................................................... 42
MAINT5: Maintenance Function Control Register 5...................................................... 42
MAINT6: Maintenance Function Control Register 6...................................................... 42
INTM0: Interrupt Mask Register 0 ................................................................................. 43
INTM1: Interrupt Masked Register 1 ............................................................................. 44
INTES: Interrupt Trigger Edge Select Register ............................................................. 45
5
5 Page 
SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL
TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name Type Pin No.
Description
INT O
20 INT: Interrupt Request
In software control mode, this pin outputs the general interrupt request for all interrupt sources. These interrupt sources can be
masked individually via registers (INTM0, 14H) and (INTM1, 15H). The interrupt status is reported via the registers (INTS0,
19H) and (INTS1, 1AH).
Output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by setting
INT_PIN[1:0] (GCF, 02H).
RXTXM0
SCLK
I
I
RXTXM0
See RXTXM1 above.
25 SCLK: Shift Clock
In serial microcontroller interface mode, this signal is the shift clock for the serial interface. Configuration data on SDI pin is sam-
pled on the rising edge of SCLK. Configuration and status data on SDO pin is clocked out of the device on the falling edge of
SCLK if SCLKE pin is high, or on the rising edge of SCLK if SCLKE pin is low.
ALE ALE: Address Latch Enable
In parallel microcontroller interface mode with multiplexed Intel interface, the address on AD[7:0] is sampled into the device on
the falling edge of ALE.
AS AS: Address Strobe
In parallel microcontroller interface mode with multiplexed Motorola interface, the address on AD[7:0] is latched into the device
on the falling edge of AS.
LP1
SDI I
LP[1:0]: Loopback mode select
When the chip is configured by hardware, this pin is used to select loopback operation modes (Inband Loopback is not provided
in hardware control mode)
• 00= no loopback
• 01= analog loopback
• 10= digital loopback
• 11= remote loopback
24 SDI: Serial Data Input
In serial microcontroller interface mode, this signal is the input data to the serial interface. Configuration data at SDI pin is sam-
pled by the device on the rising edge of SCLK.
WR WR: Write Strobe
In Intel parallel multiplexed interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. The data on
AD[7:0] is sampled into the device in a write operation.
R/W R/W: Read/Write Select
In Motorola parallel multiplexed interface mode, this pin is low for write operation and high for read operation.
LP0 LP0
See LP1 above.
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT82V2081.PDF ] | |
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