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PDF IDT82V2054 Data sheet ( Hoja de datos )
| Número de pieza | IDT82V2054 | |
| Descripción | QUAD E1 SHORT HAUL LINE INTERFACE UNIT | |
| Fabricantes | IDT | |
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QUAD E1 SHORT HAUL LINE
INTERFACE UNIT
IDT82V2054
FEATURES
! Fully integrated quad E1 short haul line interface which
supports 120 Ω twisted pair and 75 Ω coaxial applications
! Selectable Single Rail mode or Dual Rail mode and AMI or
HDB3 encoder/decoder
! Built-in transmit pre-equalization meets G.703
! Selectable transmit/receive jitter attenuator meets ETSI CTR12/
13, ITU G.736, G.742 and G.823 specifications
! SONET/SDH optimized jitter attenuator meets ITU G.783
mapping jitter specification
! Digital/Analog LOS detector meets ITU G.775 and ETS 300 233
! ITU G.772 non-intrusive monitoring for in-service testing for
any one of channel 1 to channel 3
! Low impedance transmit drivers with high-Z
! Selectable hardware and parallel/serial host interface
! Local and Remote Loopback test functions
! Hitless Protection Switching (HPS) for 1 + 1 protection without
relays
! JTAG boundary scan for board test
! 3.3 V supply with 5 V tolerant I/O
! Low power consumption
! Operating temperature range: -40°C to +85°C
! Available in 144-pin Thin Quad Flat Pack (TQFP) and 160-pin
Plastic Ball Grid Array (PBGA) packages
Green package options available
FUNCTIONAL BLOCK DIAGRAM
RTIPn
RRINGn
TTIPn
TRINGn
G.772
Monitor
Analog
Peak
Loopback Detector
Line
Driver
Clock
Generator
Slicer
LOS
Detector
CLK&Data
Recovery
(DPLL)
Digital
Loopback
One of Four Identical Channels
Jitter
Attenuator
B8ZS/
HDB3/AMI
Decoder
Remote
Loopback
AIS
Detector
Waveform
Shaper
Jitter
Attenuator
B8ZS/
HDB3/AMI
Encoder
Transmit
All Ones
Control Interface
Register
File
JTAG TAP
LOSn
RCLKn
RDn/RDPn
CVn/RDNn
TCLKn
TDn/TDPn
BPVIn/TDNn
VDDIO
VDDT
VDDD
VDDA
Figure-1 Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2005 Integrated Device Technology, Inc.
1
September 22, 2005
DSC-6778/-
1 page  
IDT82V2054
QUAD E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
TCLK0
TCLK1
TCLK2
TCLK3
Pin No.
Type
TQFP144 PBGA160
Description
TCLKn: Transmit Clock for Channel 0~3
The clock of 2.048 MHz for transmit is input on this pin. The transmit data at TDn/TDPn or TDNn is sam-
pled into the device on the falling edges of TCLKn.
Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in Transmit All
Ones (TAOS) state (when MCLK is clocked). In TAOS state, the TAOS generator adopts MCLK as the
clock reference.
If TCLKn is low, the corresponding transmit channel is set into power down state, while driver output ports
become high-Z.
Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as the fol-
lows:
MCLK
TCLKn
Transmit Mode
36
N1
Clocked
Clocked
Normal operation
I
29
81
L1
L14
Clocked
High (≥
16 MCLK)
Transmit All Ones (TAOS) signals to the line side in the corresponding
transmit channel.
74 N14 Clocked Low (≥ 64 MCLK) The corresponding transmit channel is set into power down state.
TCLKn is clocked Normal operation
TCLKn is high Transmit All Ones (TAOS) signals to the line side
(≥ 16 TCLK1) in the corresponding transmit channel.
High/Low
TCLK1 is clocked
TCLKn is low
(≥ 64 TCLK1)
Corresponding transmit channel is set into power
down state.
The receive path is not affected by the status of TCLK1. When MCLK
is high, all receive paths just slice the incoming data stream. When
MCLK is low, all the receive paths are powered down.
High/Low
TCLK1 is unavail-
able.
All four transmitters (TTIPn & TRINGn) will be in high-Z.
RD0/RDP0
RD1/RDP1
RD2/RDP2
RD3/RDP3
CV0/RDN0
CV1/RDN1
CV2/RDN2
CV3/RDN3
O
High-Z
40
33
77
70
41
34
76
69
RDn: Receive Data for Channel 0~3
In Single Rail mode, the received NRZ data is output on this pin. The data is decoded by AMI or HDB3 line
code rule.
CVn: Code Violation for Channel 0~3
In Single Rail mode, the bipolar violation, code violation and excessive zeros will be reported by driving pin
P2 CVn high for a full clock cycle. However, only bipolar violation is indicated when AMI decoder is selected.
M2
M13 RDPn/RDNn: Positive/Negative Receive Data for Channel 0~3
P13 In Dual Rail Mode with clock recovery, these pins output the NRZ data. A high signal on RDPn indicates
the receipt of a positive pulse on RTIPn/RRINGn while a high signal on RDNn indicates the receipt of a
P3 negative pulse on RTIPn/RRINGn.
M3 The output data at RDn or RDPn/RDNn are clocked out on the falling edges of RCLK when the CLKE input
M12 is low, or are clocked out on the rising edges of RCLK when CLKE is high.
P12 In Dual Rail Mode without clock recovery, these pins output the raw RZ sliced data. In this data recovery
mode, the active polarity of RDPn/RDNn is determined by pin CLKE. When pin CLKE is low, RDPn/RDNn
is active low. When pin CLKE is high, RDPn/RDNn is active high.
In hardware mode, RDn or RDPn/RDNn will remain active during LOS. In host mode, these pins will either
remain active or insert alarm indication signal (AIS) into the receive path, determined by bit AISE in regis-
ter GCF.
RDn or RDPn/RDNn is set into high-Z when the corresponding receiver is powered down.
Pin Description
5 September 22, 2005
5 Page 
IDT82V2054
QUAD E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
IC
DNC
Pin No.
Type
TQFP144 PBGA160
Description
Others
-
93 G13 IC: Internal Connection
94 H13 Internal use. Leave it open for normal operation.
3 A1
4 A2
5 A3
6 A5
103 A7
104 A8
105 A10
106 A12
110 A13
111 A14
112 B5
113 B7
117 B8
118 B10
120 C1
-
121
123
C2
C3
DNC: Do Not Connect
124 C5
126 C7
127 C8
129 C10
130 C12
132 C13
133 C14
135 D5
136 D7
138 D8
139 D10
140 E3
141 E4
142 E11
143 E12
Pin Description
11 September 22, 2005
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT82V2054.PDF ] | |
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