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PDF IDT82V2048E Data sheet ( Hoja de datos )
| Número de pieza | IDT82V2048E | |
| Descripción | OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT | |
| Fabricantes | IDT | |
| Logotipo |  |
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OCTAL CHANNEL T1/E1/J1
SHORT HAUL LINE INTERFACE UNIT
IDT82V2048E
FEATURES:
• Eight channel T1/E1/J1 short haul line interfaces
• Supports HPS (Hitless Protection Switching) for 1+1 protection
- High impedance setting for line drivers
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 215-1 PRBS polynomials for E1
without external relays
- QRSS (Quasi Random Sequence Signals) generation and detection
• Programmable T1/E1/J1 switchability allowing one bill of ma-
with 220-1 QRSS polynomials for T1/J1
terial for any line condition
- 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS
• Single 3.3 V power supply with 5 V tolerance on digital interfaces
error counter
• Meets or exceeds specifications in
- Analog loopback, Digital loopback, Remote loopback and Inband
- ANSI T1.102, T1.403 and T1.408
loopback
- ITU I.431, G.703,G.736, G.775 and G.823
• Adaptive receive sensitivity up to -20 dB
- ETSI 300-166, 300-233 and TBR 12/13
• Non-intrusive monitoring per ITU G.772 specification
- AT&T Pub 62411
• Short circuit protection for line drivers
• Per channel software selectable on:
• LOS (Loss Of Signal) detection with programmable LOS levels
- Wave-shaping templates
• AIS (Alarm Indication Signal) detection
- Line terminating impedance (T1:100 Ω, J1:110 Ω, E1:75 Ω/120 Ω) • JTAG interface
- Adjustment of arbitrary pulse shape
• Supports serial control interface, Motorola and Intel Non-Multi-
- JA (Jitter Attenuator) position (receive path or transmit path)
plexed interfaces
- Single rail/dual rail system interfaces
• Package:
- B8ZS/HDB3/AMI line encoding/decoding
IDT82V2048E: 208-pin PQFP and 208-pin PBGA
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
DESCRIPTION:
The IDT82V2048E can be configured as an octal T1, octal E1 or octal
J1 Line Interface Unit. The IDT82V2048E performs clock/data recovery,
AMI/B8ZS/HDB3 line decoding and detects and reports the LOS condi-
tions. An integrated Adaptive Equalizer is available to increase the receive
sensitivity and enable programming of LOS levels. In transmit path, there
is an AMI/B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter
Attenuator for each channel, which can be placed in either the receive path
or the transmit path. The Jitter Attenuator can also be disabled. The
IDT82V2048E supports both Single Rail and Dual Rail system interfaces
and both serial and parallel control interfaces. To facilitate the network
maintenance, a PRBS/QRSS generation/detection circuit is integrated in
each channel, and different types of loopbacks can be set on a per channel
basis. Four different kinds of line terminating impedance, 75Ω, 100 Ω, 110
Ω and 120 Ω are selectable on a per channel basis. The chip also provides
driver short-circuit protection and supports JTAG boundary scanning.
The IDT82V2048E can be used in SDH/SONET, LAN, WAN, Routers,
Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay
Access Devices, CSU/DSU equipment, etc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
2003 Integrated Device Technology, Inc. All rights reserved.
1
August 2004
DSC-6532/-
1 page  
OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
LIST OF TABLES
INDUSTRIAL
TEMPERATURE RANGES
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
Table-18
Table-19
Table-20
Table-21
Table-22
Table-23
Table-24
Table-25
Table-26
Table-27
Table-28
Table-29
Table-30
Table-31
Table-32
Table-33
Table-34
Table-35
Table-36
Table-37
Table-38
Table-39
Table-40
Pin Description .............................................................................................................. 10
Transmit Waveform Value For E1 75 Ω ........................................................................ 17
Transmit Waveform Value For E1 120 Ω ...................................................................... 18
Transmit Waveform Value For T1 0~133 ft................................................................... 18
Transmit Waveform Value For T1 133~266 ft............................................................... 18
Transmit Waveform Value For T1 266~399 ft............................................................... 18
Transmit Waveform Value For T1 399~533 ft............................................................... 19
Transmit Waveform Value For T1 533~655 ft............................................................... 19
Transmit Waveform Value For J1 0~655 ft ................................................................... 19
Impedance Matching for Transmitter ............................................................................ 20
Impedance Matching for Receiver ................................................................................ 21
Criteria of Starting Speed Adjustment........................................................................... 24
LOS Declare and Clear Criteria, Adaptive Equalizer Disabled ..................................... 25
LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ...................................... 26
AIS Condition ................................................................................................................ 26
Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 27
EXZ Definition ............................................................................................................... 30
Interrupt Event............................................................................................................... 34
Global Register List and Map........................................................................................ 36
Per Channel Register List and Map .............................................................................. 37
ID: Chip Revision Register ............................................................................................ 38
RST: Reset Register ..................................................................................................... 38
GCF0: Global Configuration Register 0 ........................................................................ 38
GCF1: Global Configuration Register 1 ........................................................................ 39
INTCH: Interrupt Channel Indication Register............................................................... 39
GPIO: General Purpose IO Pin Definition Register....................................................... 39
JACF: Jitter Attenuator Configuration Register ............................................................. 40
TCF0: Transmitter Configuration Register 0 ................................................................. 41
TCF1: Transmitter Configuration Register 1 ................................................................. 41
TCF2: Transmitter Configuration Register 2 ................................................................. 42
TCF3: Transmitter Configuration Register 3 ................................................................. 42
TCF4: Transmitter Configuration Register 4 ................................................................. 42
RCF0: Receiver Configuration Register 0..................................................................... 43
RCF1: Receiver Configuration Register 1..................................................................... 43
RCF2: Receiver Configuration Register 2..................................................................... 44
MAINT0: Maintenance Function Control Register 0...................................................... 45
MAINT1: Maintenance Function Control Register 1...................................................... 45
MAINT2: Maintenance Function Control Register 2...................................................... 46
MAINT3: Maintenance Function Control Register 3...................................................... 46
MAINT4: Maintenance Function Control Register 4...................................................... 46
5
5 Page 
OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL
TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
PQFP208 PBGA208
Transmit and Receive Digital Data Interface
TD1/TDP1
TD2/TDP2
TD3/TDP3
TD4/TDP4
TD5/TDP5
TD6/TDP6
TD7/TDP7
TD8/TDP8
TDN1
TDN2
TDN3
TDN4
TDN5
TDN6
TDN7
TDN8
Input
155
149
143
137
127
121
115
109
154
148
142
136
126
120
114
108
B15 TDn: Transmit Data for Channel 1~8
D15 In Single Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDn is sampled
E15 into the device on the active edge of TCLKn. The active edge of TCLKn is selected by the TCLK_SEL
G15 bit (TCF0, 02H...). Data is encoded by AMI, HDB3 or B8ZS line code rules before being transmitted to
J15 the line. In this mode, TDNn should be connected to ground.
L15
N15 TDPn/TDNn: Positive/Negative Transmit Data for Channel 1~8
R16 In Dual Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDPn/TDNn is sam-
pled into the device on the active edge of TCLKn. The active edge of the TCLKn is selected by the
C14 TCLK_SEL bit (TCF0, 02H...) The line code in Dual Rail Mode is as follows:
D14
F13
TDPn TDNn
Output Pulse
G14 0 0 Space
J14 0 1 Positive Pulse
L14
M13
1 0 Negative Pulse
P15 1 1 Space
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
TCLK8
RD1/RDP1
RD2/RDP2
RD3/RDP3
RD4/RDP4
RD5/RDP5
RD6/RDP6
RD7/RDP7
RD8/RDP8
CV1/RDN1
CV2/RDN2
CV3/RDN3
CV4/RDN4
CV5/RDN5
CV6/RDN6
CV7/RDN7
CV8/RDN8
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
Input
Output
Output
156
150
144
138
129
122
116
110
152
146
140
134
124
118
112
106
151
145
139
132
123
117
111
105
153
147
141
135
125
119
113
107
A15 TCLKn: Transmit Clock for Channel 1~8
C16 These pins input 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit
E16 data on TDn/TDPn or TDNn is sampled into the device on the active edge of TCLKn. If TCLKn is
G16 missing1 and the TCLKn missing interrupt is not masked, an interrupt will be generated.
J16
L16
N16
T16
B16 RDn: Receive Data for Channel 1~8
E14 In Single Rail Mode, the NRZ receive data is output on these pins. Data is decoded according to AMI,
F15 HDB3 or B8ZS line code rules. The active level on RDn pin is selected by the RD_INV bit (RCF0,
H14 07H...).
K14
M15 CVn: Code Violation for Channel 1~8
N14 In Single Rail Mode, the BPV/CV errors in received data streams will be reported by driving pin CVn
P14 to high level for a full clock cycle. The B8ZS/HDB3 line code violation can be indicated when the B8ZS/
HDB3 decoder is enabled. When AMI decoder is selected, the bipolar violation can be indicated.
C15
E13 RDPn/RDNn: Positive/Negative Receive Data for Channel 1~8
F14 In Dual Rail Mode with Clock & Data Recovery (CDR), these pins output the NRZ data with the recov-
H13 ered clock. An active level on RDPn indicates the receipt of a positive pulse on RTIPn/RRINGn while
K13 an active level on RDNn indicates the receipt of a negative pulse on RTIPn/RRINGn. The active level
M14 on RDPn/RDNn is selected by the RD_INV bit (RCF0, 07H...). When CDR is disabled, these pins
N13 directly output the raw RZ sliced data. The output data on RDn and RDPn/RDNn is updated on the
R15 active edge of RCLKn.
A16 RCLKn: Receive Clock for Channel 1~8
D16 These pins output 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS
F16 conditions, if AISE bit (MAINT0, 0AH...) is ‘1’, RCLKn is derived from MCLK.
H15 In clock recovery mode, these pins provide the clock recovered from the signal received on RTIPn/
K15 RRINGn. The receive data (RDn in Single Rail Mode or RDPn/RDNn in Dual Rail Mode) is updated on
M16 the active edge of RCLKn. The active edge is selected by the RCLK_SEL bit (RCF0, 07H...).
P16 If clock recovery is bypassed, RCLKn is the exclusive OR(XOR) output of the Dual Rail sliced data
T15 RDPn and RDNn. This signal can be used in the applications with external clock recovery circuitry.
Notes:
1. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 clock cycles.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT82V2048E.PDF ] | |
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