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PDF TDF8555J Data sheet ( Hoja de datos )
| Número de pieza | TDF8555J | |
| Descripción | I2C-bus controlled 4 x 45W power amplifier and multiple voltage regulator | |
| Fabricantes | NXP Semiconductors | |
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TDF8555J
I2C-bus controlled 4 45 W power amplifier and multiple
voltage regulator
Rev. 1.1 — 15 September 2011
Product data sheet
1. General description
The TDF8555J is one of a new generation of complementary quad Bridge-Tied Load
(BTL) audio power amplifiers with full I2C-bus controlled diagnostics, multiple voltage
regulator and two power switches intended for automotive applications.
The TDF8555J can operate at a battery voltage as low as 6 V making this amplifier
suitable for stop/start-car operation. The amplifier uses a complementary DMOS output
stage in a Silicon-On-Insulator (SOI)-based BCD process. The DMOS output stage
ensures a high power output signal with perfect sound quality. The SOI-based BCD
process ensures a robust amplifier, where latch-up cannot occur, with good separation
between the four independent channels with every component isolated and without
substrate currents.
The multiple voltage regulator comprises four programmable voltage regulators, two
standby regulators and two power switches.
The TDF8555J is soft- and hardware downwards-compatible with its predecessor
TDF8551J.
The TDF8555J includes features, such as selectable undervoltage for stop/start-cars
which can be selected with additional I2C-bus instruction bytes. If these additional bytes
are not sent, the TDF8555J has the same functionality as its predecessor IPAS
TDF8551J.
2. Features and benefits
Amplifier
Stop/start-car prepared: keeps operating without audible disturbance during
engine start at a battery voltage as low as 6 V
I2C-bus mode (3.3 V and 5 V compliant)
Can drive 2 or 4 loads
Speaker fault detection
Start-up diagnostics with load detection: open, short, present; filtered for door-slam
and chatter relays
AC load (tweeter) detection with low and high current mode
Gain select after start-up without audible disturbance
Programmable gain (26 dB and 16 dB), independently programmable for the front
and rear channels
Line driver mode (16 dB and mid-tap voltage 0.25VP for stop/start-cars)
Programmable clip detection: 2 %, 5 % or 10 %
1 page  
NXP Semiconductors
5. Block diagram
TDF8555J
4 45 W power amplifier with multiple voltage regulator
36
BUCAP
BACKUP
MECHANISM
35
VP
VDCDC
26
REFERENCE
VOLTAGE
ENABLE
LOGIC
LOADDUMP
PROTECTION
TEMPERATURE
PROTECTION
REGULATOR 2
REGULATOR 6
REGULATOR 1
REGULATOR 3
REGULATOR 4
REGULATOR 5
SWITCH 1
SWITCH 2
SDA
SCL
STB
2
4
22
STANDBY/MUTE
I2C-BUS
INTERFACE
TDF8555J
CLIP DETECT/DIAGNOSTIC
37
REG2
28
REG6
30 REG1
31 REG3
33 REG4
34
REG5
29
SW1
27
SW2
32 GND
20
VP1
6
VP2
25
DIAG
IN1 11
12
IN2
15
IN3
14
IN4
VP
MUTE
26 dB/
16 dB
MUTE
26 dB/
16 dB
MUTE
26 dB/
16 dB
MUTE
26 dB/
16 dB
PROTECTION/
DIAGNOSTIC
PROTECTION/
DIAGNOSTIC
PROTECTION/
DIAGNOSTIC
PROTECTION/
DIAGNOSTIC
9
OUT1+
7 OUT1-
5
OUT2+
3 OUT2-
17 OUT3+
19
OUT3-
21
OUT4+
23 OUT4-
Fig 1. Block diagram
TDF8555J
Product data sheet
10
SVR
13
SGND
16 8 1 18 24
ACGND
PGND1
PGND3
PGND2/TAB
PGND4
001aan411
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 September 2011
© NXP B.V. 2011. All rights reserved.
5 of 57
5 Page 
NXP Semiconductors
TDF8555J
4 45 W power amplifier with multiple voltage regulator
The DC input voltage follows the supply voltage slowly (SVR capacitor) to prevent audible
plops, even during engine start.
If the battery voltage drops below 6 V, low VP mute is activated. During the low VP mute
the amplifier fast mutes (approximately 400 s). When mute is completed, the capacitor
on pin ACGND and on pin SVR are both discharged to prevent audible plops. If the
battery voltage rises again above the low VP mute threshold (6 V), and there has been no
Power-On Reset (POR) (DB2[D7]) = 1, the amplifier starts automatically. The amplifier
only restarts if the SVR capacitor has been discharged to 0.7 V to prevent a start-up plop.
If the battery voltage has dropped too much that the internal registers lose their
information, a POR occurs and the amplifier will not restart automatically. Pin DIAG is
pulled LOW to indicate a POR has occurred.
The device prevents amplifier plops during engine start. To prevent plops on the amplifier
output caused by, for instance, a tuner regulator out of regulation, the voltage on pin STB
can be made zero when an engine start is detected. Pin STB activates the fast mute,
suppressing disturbances at the amplifier inputs.
The built-in low battery mute voltage default is set to 5.5 V, but can also be set to 7.2 V via
the I2C-bus.
When the low battery voltage mute is set to 7.2 V, the amplifier activates the fast mute
(400 s) and enters the same cycle when the low VP mute was set to 5.5 V: discharge of
the ACGND and SVR capacitors when the mute is completed and start-up when the
supply voltage is above 8 V, when no POR has occurred.
14
voltage
(V) 10
VP
SVR clamp voltage
7
UVP
6
3.5
DC voltage output
not filtered to ensure
headroom
Fig 4. Engine start protection
DC output voltage
SVR voltage/DC input voltage
amplifier re-start
(depends on
I2C-bus content)
t(start-Vo(off))
t(start-SVRoff)
t (s)
001aam687
7.3 POR behavior
If the supply voltage drops below 4.5 V, the content of the I2C latches cannot be
guaranteed and POR is activated at a typical VP level of 3.1 V. All latches are reset, the
amplifier is switched off and pin DIAG is pulled LOW to indicate that a POR has occurred
(DB2[D7] = 1). If IB1[D0] is set, the power-on flag is reset, pin DIAG is released and the
amplifier starts.
TDF8555J
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 September 2011
© NXP B.V. 2011. All rights reserved.
11 of 57
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