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PDF CD4068BMS Data sheet ( Hoja de datos )

Número de pieza CD4068BMS
Descripción CMOS 8 Input NAND/AND Gate
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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CD4068BMS
December 1992
CMOS 8 Input NAND/AND Gate
Features
• High Voltage Type (20V Rating)
• Medium Speed Operation
- TPHL, TPLH = 75ns (Typ.) at VDD = 10V
• Buffered Inputs and Outputs
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4068BMS NAND/AND gate provides the system designer
with direct implementation of the positive logic 8 Input NAND and
AND functions and supplements the existing family of CMOS
gates.
The CD4068BMS is supplied in these 14 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4H
H1B
H3W
Pinout
CD4068BMS
TOP VIEW
K=A·B·C·D·E·F·G·H 1
A2
B3
C4
D5
NC 6
VSS 7
14 VDD
13 J = A · B · C · D · E · F · G · H
12 H
11 G
10 F
9E
8 NC
NC = NO CONNECTION
Functional Diagram
2
A
3
B4
C
5
D
9
E
F 10
11
G
12
H
1
K
13
J
J=A·B·C·D·E·F·G·H
K=A·B·C·D·E·F·G·H
VDD = 14
VSS = 7
6, 8 = NO CONNECTION
Logic Diagram
A2
B3
C4
D5
E9
F 10
G 11
H 12
FIGURE 1. LOGIC DIAGRAM
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-985
13 J
1K
File Number 3320

1 page




CD4068BMS pdf
Specifications CD4068BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1
Note 1
OPEN
1, 6, 8, 13
GROUND
2-5, 7, 9-12
VDD
14
9V ± -0.5V
50kHz
25kHz
Static Burn-In 2
Note 1
1, 6, 8, 13
7 2-5, 9-12, 14
Dynamic Burn-
In Note 1
6, 8
7
14
1, 13
2-5, 9-12
Irradiation
Note 2
1, 6, 8, 13
7 2-5, 9-12, 14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-989

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