PDF RTL8139BL Data sheet ( Hoja de datos )

Número de pieza	RTL8139BL
Descripción	SINGLE CHIP FAST ETHERNET CONTROLLER
Fabricantes	Realtek Microelectronics
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No Preview Available ! RTL8139B(L) Preliminary REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT RTL8139B(L) 1. Features: l 128 pins QFP/LQFP l Integrated Fast Ethernet MAC, Physical chip and transceiver in one chip l 10 Mb/s and 100 Mb/s operation l Supports 10 Mb/s and 100 Mb/s N-way Auto- negotiation operation l PCI local bus single-chip Fast Ethernet controller ² Compliant to PCI Revision 2.2 ² Supports PCI clock 16.75MHz-40MHz ² Supports PCI target fast back-to-back transaction ² Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of RTL8139B(L)'s operational registers ² Supports PCI VPD (Vital Product Data) ² Supports ACPI, PCI power management ² The RTL8139BL works in 3.3V signaling environment mainly, and the RTL8139B is used in 5V signaling environment only. Both need 5-volt working voltage as power source. l Supports CardBus. The CIS can be stored in 93C56 or expansion ROM l Supports up to 128K bytes Boot ROM interface for both EPROM and Flash memory l Supports 25MHz crystal or 50MHz OSC as the internal clock source. The frequency deviation of either crystal or OSC must be within 50 PPM. l Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and Microsoft® wake-up frame) l Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse) l Supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still remains off l Supports auxiliary power auto-detect, and sets the related capability of power management 1999/7/26 1 Rev.2.4 1 page 3. Pin Assignment 84 GND 85 RTSET 86 RXIN- 87 RXIN+ 88 OEB 89 WEB 90 VDD 91 TXD- 92 TXD+ 93 GND 94 XTALSELB 95 ISOLATEB 96 VDD 97 LED2 98 LED1 99 LED0 100 MD7 101 MD6 102 MD5 RTL8139B(L) Preliminary 83 LWAKE/CSTSCHG 82 RTT2 81 RTT3 80 GND 79 X1 78 X2 77 VDD 76 PMEB 75 CLKRUNB 74 GND 73 VDD 72 VDD 71 GND 70 MA16 69 MA15 68 MA14 67 MA13 66 MA12 65 MA11 103 MD4 104 MD3 105 MD2 106 VDD 107 MD1 108 MD0 109 VDD 110 ROMCSB 111 GND 112 GND 113 GND 114 INTAB 115 RSTB 116 CLK 117 GNTB 118 REQB 119 VDD 120 AD31 121 AD30 122 AD29 123 AD28 124 GND 125 AD27 126 AD26 127 AD25 128 AD24 RTL8139B(L) 64 MA10 63 MA9 62 GND 61 MA8 60 MA7 59 VDD 58 VDD 57 MA6/9356SEL 56 GND 55 GND 54 VREF 53 MA5 52 MA4 51 MA3 50 EECS 49 MA2 48 MA1 47 MA0 46 VDD 45 AD0 44 AD1 43 AD2 42 AD3 41 AD4 40 GND 39 AD5 1 VDD 2 CBE3B 3 IDSEL 4 AD23 5 AD22 6 AD21 7 GND 8 AD20 9 AD19 10 AD18 11 AD17 12 VDD 13 AD16 14 CBE2B 15 FRAMEB 16 IRDYB 17 TRDYB 18 GND 19 DEVSELB 38 AD6 37 AD7 36 CBE0B 35 VDD 34 AD8 33 AD9 32 AD10 31 AD11 30 GND 29 AD12 28 AD13 27 AD14 26 AD15 25 VDD 24 CBE1B 23 PAR 22 SERRB 21 PERRB 20 STOPB 1999/7/26 5 Rev.2.4 5 Page 006Eh-006Fh 0070h-0071h 0072h-0073h 0074h-0075h 0076-0077h 0078h-007Bh 007Ch-007Fh 0080h 0081-0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch–0093h 0094h–009Bh 009Ch–00A3h 00A4h–00ABh 00ACh–00B3h 00B4h–00BBh 00BCh–00C3h 00C4h–00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h-00D7h 00D8h 00D9h-00EFh 00F0h-00F3h 00F4h-00F7h 00F8h-00FBh 00FCh-00FFh R R/W R R/W - R/W R/W R/W - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - R/W R/W R W FCSC NWAYTR REC CSCR - PHY1_PARM TW_PARM PHY2_PARM - CRC0 CRC1 CRC2 CRC3 CRC4 CRC5 CRC6 CRC7 Wakeup0 Wakeup1 Wakeup2 Wakeup3 Wakeup4 Wakeup5 Wakeup6 Wakeup7 LSBCRC0 LSBCRC1 LSBCRC2 LSBCRC3 LSBCRC4 LSBCRC5 LSBCRC6 LSBCRC7 FLASH Config5 - FER FEMR FPSR FFER RTL8139B(L) Preliminary False Carrier Sense Counter N-way Test Register RX_ER Counter CS Configuration Register Reserved. PHY parameter 1 Twister parameter PHY parameter 2 Reserved Power Management CRC register0 for wakeup frame0 Power Management CRC register1 for wakeup frame1 Power Management CRC register2 for wakeup frame2 Power Management CRC register3 for wakeup frame3 Power Management CRC register4 for wakeup frame4 Power Management CRC register5 for wakeup frame5 Power Management CRC register6 for wakeup frame6 Power Management CRC register7 for wakeup frame7 Power Management wakeup frame0 (64bit) Power Management wakeup frame1 (64bit) Power Management wakeup frame2 (64bit) Power Management wakeup frame3 (64bit) Power Management wakeup frame4 (64bit) Power Management wakeup frame5 (64bit) Power Management wakeup frame6 (64bit) Power Management wakeup frame7 (64bit) LSB of the mask byte of wakeup frame0 within offset 12 to 75 LSB of the mask byte of wakeup frame1 within offset 12 to 75 LSB of the mask byte of wakeup frame2 within offset 12 to 75 LSB of the mask byte of wakeup frame3 within offset 12 to 75 LSB of the mask byte of wakeup frame4 within offset 12 to 75 LSB of the mask byte of wakeup frame5 within offset 12 to 75 LSB of the mask byte of wakeup frame6 within offset 12 to 75 LSB of the mask byte of wakeup frame7 within offset 12 to 75 Flash memory read/write register Configuration register 5(rev.F)/Reserved (rev.D) Reserved Function Event Register (Cardbus only) Function Event Mask Register (CardBus only) Function Present State Register (CardBus only) Function Force Event Register (CardBus only) 5.1 Receive Status Register in Rx packet header Bit R/W Symbol Description 15 R MAR Multicast Address Received: Set to 1 indicates that a multicast packet is received. 14 R PAM Physical Address Matched: Set to 1 indicates that the destination address of this packet matches the value written in ID registers. 13 R BAR Broadcast Address Received: Set to 1 indicates that a broadcast packet is received. BAR, MAR bit will not be set simultaneously. 1999/7/26 11 Rev.2.4 11 Page

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