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PDF CD4066BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4066BMS | |
| Descripción | CMOS 4-Bit Magnitude Comparator | |
| Fabricantes | Intersil Corporation | |
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CD4066BMS
December 1992
CMOS Quad Bilateral Switch
Features
Description
• For Transmission or Multiplexing of Analog or Digital
Signals
• High Voltage Types (20V Rating)
• 15V Digital or ±7.5V Peak-to-Peak Switching
• 125Ω Typical On-State Resistance for 15V Operation
• Switch On-State Resistance Matched to Within 5Ω
Over 15V Signal Input Range
• On-State Resistance Flat Over Full Peak-to-Peak Sig-
nal Range
• High On/Off Output Voltage Ratio
- 80dB Typ. at FIS = 10kHz, RL = 1kΩ
• High Degree of Linearity: <0.5% Distortion Typ. at
FIS = 1kHz, VIS = 5Vp-p, VDD - VSS ≥ 10V, RL = 10kΩ
• Extremely Low Off-State Switch Leakage Resulting in
Very Low Offset Current and High Effective Off-State
Resistance: 10pA Typ. at VDD - VSS = 10V, TA = +25oC
• Extremely High Control Input Impedance (Control Cir-
cuit Isolated from Signal Circuit): 1012Ω Typ.
• Low Crosstalk Between Switches: -50dB Typ. at FIS =
8MHz, RL = 1kΩ
• Matched Control Input to Signal Output
Capacitance: Reduces Output Signal Transients
CD4066BMS is a quad bilateral switch intended for the
transmission or multiplexing of analog or digital signals. It is
pin for pin compatible with CD4016B, but exhibits a much
lower on state resistance. In addition, the on-state resistance
is relatively constant over the full input signal range.
The CD4066BMS consists of four independent bilateral
switches. A single control signal is required per switch. Both
the p and the n device in a given switch are biased on or off
simultaneously by the control signal. As shown in Figure 1,
the well of the n channel device on each switch is either tied
to the input when the switch is on or to VSS when the switch
is off. This configuration eliminates the variation of the switch
transistor threshold voltage with input signal, and thus keeps
the on-state resistance low over the full operating signal
range.
The advantages over single channel switches include peak
input signal voltage swings equal to the full supply voltage,
and more constant on-state impedance over the input signal
range. For sample and hold applications, however, the
CD4016B is recommended.
The CD4066BMS is supplied in these 14-lead outline pack-
ages:
Braze Seal DIP H4Q
Frit Seal DIP
H1B
Ceramic Flatpack H3W
• Frequency Response, Switch on = 40MHz (Typ.)
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
“B” Series CMOS Devices”
Pinout
Applications
• Analog Signal Switching/Multiplexing
- Signal Gating
- Modulator
- Squelch Control
- Demodulator
- Chopper
- Commutating Switch
• Digital Signal Switching/Multiplexing
CD4066BMS
TOP VIEW
IN/OUT A 1
OUT/IN A 2
OUT/IN B 3
IN/OUT B 4
CONT B 5
CONT C 6
VSS 7
14 VDD
13 CONT A
12 CONT D
11 IN/OUT D
10 OUT/IN D
9 OUT/IN C
8 IN/OUT C
• Transmission Gate Logic Implementation
• Analog to Digital & Digital to Analog Conversion
• Digital Control of Frequency, Impedance, Phase, and
Analog Signal Gain
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-966
File Number 3319
1 page  
Specifications CD4066BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
Static Burn-In 1 (Note 1)
OPEN
2, 3, 9, 10
GROUND
1, 4-8, 11-13
VDD
14
9V ± -0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 2 (Note 1)
2, 3, 9, 10
7 1, 4-6, 8, 11-14
Dynamic Burn-In (Note 1)
-
7
14
2, 3, 9, 10
5, 6, 12, 13
1, 4, 8, 11
Irradiation (Note 2)
2, 3, 9, 10
7 1, 4-6, 8, 11-14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
Functional Diagram
IN/OUT
SIG A
OUT/IN
1
2
OUT/IN
SIG B
IN/OUT
3
4
CONTROL B 5
SW
A
SW
D
SW
B
14 VDD
13 CONTROL A
12 CONTROL D
11 IN/OUT
SIG D
10 OUT/IN
TRUTH TABLE EACH SWITCH
INPUT
OUTPUT
VC VIS VOS
100
111
0 0 Open
0 1 Open
Positive Logic: Switch ON VC = “1”
Switch OFF VC = “0”
CONTROL C 6
9 OUT/IN
SW
C
SIG C
VSS 7
8 IN/OUT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
970
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