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PDF CD4063BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4063BMS | |
| Descripción | CMOS 4-Bit Magnitude Comparator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4063BMS
December 1992
CMOS 4-Bit Magnitude Comparator
Features
Pinout
• High Voltage Type (20V Rating)
• Expansion to 8, 12, 16 . . . 4N Bits by Cascading Units
• Medium Speed Operation
- Compares Two 4-Bit Words in 250ns (Typ.) at 10V
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Full Package Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
CD4063BMS
TOP VIEW
B3 1
(A < B) IN 2
(A = B) IN 3
(A > B) IN 4
(A > B) OUT 5
(A = B) OUT 6
(A < B) OUT 7
VSS 8
16 VDD
15 A3
14 B2
13 A2
12 A1
11 B1
10 A0
9 B0
Functional Diagram
Applications
• Servo Motor Controls
• Process Controllers
Description
CD4063BMS is a 4-bit magnitude comparator designed for use
in computer and logic applications that require the comparison of
two 4-bit words. This logic circuit determines whether one 4-bit
word (Binary or BCD) is “less than”, “equal to”, or “greater than” a
second 4-bit word.
The CD4063BMS has eight comparing inputs (A3, B3, through
A0, B0), three outputs (A < B, A = B, A > B) and three cascading
inputs (A < B, A = B, A > B) that permit systems designers to
expand the comparator function to 8, 12, 16 . . . 4N bits. When a
single CD4063BMS is used, the cascading inputs are connected
as follows: (A < B) = low, (A = B) = high, (A > B) = low.
For words longer than 4 bits, CD4063BMS devices may be cas-
caded by connecting the outputs of the less significant compara-
tor to the corresponding cascading inputs of the more significant
comparator. Cascading inputs (A < B, A = B, and A > B) on the
least significant comparator are connected to a low, a high, and a
low level, respectively.
The CD4063BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1E
H6W
4
WORD A
A>B
CASCADING
INPUTS
A=B
A<B
4
WORD B
A>B
A=B
A<B
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-958
File Number 3318
1 page  
Specifications CD4063BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
METHOD
GROUP A SUBGROUPS
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 5% parametric, 3% functional; cumulative for static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
TEST
METHOD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9, Deltas
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1
Note 1
5-7
1, 2, 4, 8-15
3, 16
Static Burn-In 2
Note 1
5-7
3, 8 1, 2, 4, 9-16
Dynamic Burn-
-
1, 2, 4, 8, 10, 11,
3, 16
In Note 1
13
5-7
12, 15
9, 14
Irradiation
Note 2
5-7
3, 8 1, 2, 4, 9-16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
VDD
A0 A1 A2 A3
A4 A5 A6 A7
CD4063
(A < B) IN
(A = B) IN
(A > B) IN
(A < B) OUT
(A = B) OUT
(A > B) OUT
CD4063
A8 A9 A10 A11
CD4063
B0 B1 B2 B3
B4 B5 B6 B7
B8 B9 B10 B11
tP TOTAL = tP (COMPARE INPUTS) + 2 x tP (CASCADE INPUTS), AT VDD = 10V
(3 STAGES)
= 250 + (2 x 200) = 650ns (TYP.)
FIGURE 1. TYPICAL SPEED CHARACTERISTICS OF A 12-BIT COMPARATOR
7-962
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CD4063BMS.PDF ] | |
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