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PDF TC55257PL-10 Data sheet ( Hoja de datos )

Número de pieza TC55257PL-10
Descripción STATIC RAM
Fabricantes Toshiba Semiconductor 
Logotipo Toshiba Semiconductor Logotipo



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No Preview Available ! TC55257PL-10 Hoja de datos, Descripción, Manual

32,768 WORD X 8 BIT CMOS STATIC RAM
SILICON GATE CMOS
TC55257 PL-S5, TC55257 P-l O/PL-l 0
TC55257 P-12/PL-12
IDESCRIPTION I
The TCSS257P is 262,144 bit static random access memory organized as 32,768 words
by 8 bits using CMOS technology, and operated from a single 5V supply. Advanced
circuit techniques provide both high speed and low power features with a operating
current of 5mA/MHz(Typ.) and minimum cycle time of 85ns.
lfuen CE is a logical high, the device is placed in low power standby mode in
which standby current is 2~A typically. The TCSS257P has two control inputs. Chip
enable (CE) allow for device selection and data retention control, and an output
enable input (OE) provides fast memory access. Thus the TCSS2S7P is suitable for use
in various microprocessor application systems where high speed, low power, and battery
back up are required.
The TCSS257P is offered in a dual-in-line 28 pin standard plastic package.
i FEATURES I
• Low Power Dissipation
27 .St:Jtl/:lliz(~!a:<.) Operating
• Standby Current
lOOuA(Max.): TC55257PL-85/
PL-IO/
PL-12
,laA(Max.); TC55257P-IOI
P-12
• SV Single Power Supply
• Power Down Feature: ~
I IPHI COilNECTImJ (TOP VIE~J)
AI ..
AI:':
A7
Ad
A5
A..
A.3
A2
Ai
AC,
I/O 1
I/O:':
1./0.3
GUD
1 ..
"DD
27 W'N
26 Al3
25 .-\8
24- A',)
23
22
All
or;
21 A10
20 CZ
19 1./08
18 I/O 7
17 I/O 6
Iii I/O 5
15 I/O ..
• Data Retention Supply Voltage: 2.0'" S.SV
----------• :\ccess Time
TC55257PL-85 TC55257P-10 TC55257P-12
TC55257PL-10 TC55257PL- 12
Access Tille (Max. )
85ns
lOOns
120ns
CE Access Time (Nax. )
85ns
lOOns
120ns
Output Eo.able T i.e (M.ax. )
400s
SOns
60ns
• Directly TTL Compatible: All Inputs and Outputs
• Standard 28 pin DIP
IIBLOCK DIAGRAi·:
A5 --aVDD
A6 -----0 QND
A7 MEMORY CELL
A8 ARRAY
A9 512 x 32-16
All
.-\12
(2621H)
Al3
Al4-
I/O1
PHI NAMES
AO '" A14
'[?/W
OE
CE
1/01 '" 1/08
VDO
GNO
Address Inputs
Read/Write Control Input
Output Enable Input
Chip Enable Input
Data Input/Output
PotoJer (+SV)
Ground
vos
C E o--~I>-- C E
- 8-91 -

1 page




TC55257PL-10 pdf
TC55257P~85, TC55257~10/P~10
TC55257 P-12/PL-12
TIMING WAVEFORMS
READ CYCLE (1)
Vla-~:~I~ADDRESSES VIL-
__ _I~~~ _________________________~
~_ _ _ _ _tn=';=C_ _ _ _ _ _~
VIH -
VIL-~~~~~--------~--------~~~~~~~~~~~
VIH -
VIL-~~~~wr~------~-------L~~~~~~~~~~~
DOUT
CUTFUT DATA VALID
I'JRITE CYCLE 1 (4) (R/l~ Controlled Hrite)
twc
ADDRESSES
VIa - ---~--~~~~'n.
VIL -
twp
VIH -
CE
VIL -
DOtI!
DIN VIa -
VIL -
tocw
tDS
DATA IN STABLE
- 8-95 -

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