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PDF TC5565AFL-10 Data sheet ( Hoja de datos )

Número de pieza TC5565AFL-10
Descripción Static RAM
Fabricantes Toshiba Semiconductor 
Logotipo Toshiba Semiconductor Logotipo



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No Preview Available ! TC5565AFL-10 Hoja de datos, Descripción, Manual

TOSHIBA MOS MEMORY PRODUCTS
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
DESCRIPTION
The TC5565APL/AFL is 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology, and
operates from a single 5V supply. Advanced circuit techniques provide both high speed and low power features with a maximum
operating current of 5mA/MHz and maximum access time of 100ns/120ns/150ns.
When CE2 is a logical low or \CEl is a logical high, the device is placed in low power standby mode in which standby current is 2uA
typically. The TC5565APL/AFL has three control inputs. Two chip enable (\CE1, CE2) allow for device selection and data retention
control, and an output enable input (\OE) provides fast memory access. Thus the TC5565APL/AFL is suitable for use in various
microprocessor application systems where high speed, low power, and battery back up are required.
The TC5565APL also features pin compatibility with the 64K bit EPROM (TMM2764D).
RAM and EPROM are then interchangeable in the same socket, resulting in flexibility in the definition of the quantity of RAM versus
EPROM in microprocessor application systems. The TC5565APL is offered in a dual-in-line 28 pin standard plastic package. The
TC5565AFL is offered in 28 pin mini Flat Package.
FEATURES
Directly TTL Compatible
Low Power Dissipation
: All Inputs and Outputs
27.5mW/MHz(Max.) operating
Pin Compatible with 2764 type EPROM
Standby Current: 100uA(Max.) Ta=70°C
TC5565APL Family (Package Type)
Access Time
TC5565APL/AFL-10 : 100ns(Max.)
Package Type
Device Name
TC5565APL/AFL-12 : 120ns(Max.)
600 mil DIP
TC5565APL
TC5565APL/AFL-15 : 150ns(Max.)
5V Single Power Supply -
Power Down Features: CE2, \CE1
Fully Static Operation
Data Retention Supply Voltage: 2.0-5.5V
300 mil DIP
*TC5563APL
(Slim Package)
Flat Package
TC5565AFL
(SOP)
* See TC5563APL Technical Data.
PIN CONNECTION (TOP VIEW)
BLOCK DIAGRAM
AO-A12
R/W
\OE
\CE1, CE2
I/O1 – I/O8
VDD
GND
N.C.
Address Inputs
Read/Write Control Input
Output Enable Input
Chip Enable Inputs
Data Input/Output
Power (+5V)
Ground
No Connection

1 page




TC5565AFL-10 pdf
TIMING WAVEFORMS
READ CYCLE (1)
TC5565APL-10, TC5565APL-12, TC5565APL-15
TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
WRITE CYCLE 1 (4) (R/W Controlled Write)

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