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PDF TC5563APL-12L Data sheet ( Hoja de datos )

Número de pieza TC5563APL-12L
Descripción CMOS Static RAM
Fabricantes Toshiba 
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No Preview Available ! TC5563APL-12L Hoja de datos, Descripción, Manual

TOSHIBA MOS MEMORY PRODUCT
8,192 WORD X 8 BIT
CMOS STATIC RAM
SILICON GATE CMOS
TC5563APl-10l, TC5563APl-12l
TC5563APl-15l
DESCRIPTION
The TC5563APL is 65,536 bit static random
access memory organized as 8,192 words by 8 bits
using CMOS technology, and operates from a single
5V supply. Advanced circuit techniques provide both
high speed and low power features with a maximum
operating current of 5mA/MHz and maximum
access time of 1OOns/120ns/150ns. When CE2 is a
logical low or CE 1 is a logical high, the device is
placed in low power standby mode in which standby
current is O. 6J1.A typically. The TC5563APL has three
control inputs. Two chip enables (CE1, CE2) allow for
device selection and data retention control, and an
output enable input (OE) provides fast memory
PRELIMINARY
access. Thus the TC5563APL is suitable for use in
various microprocessor applicatior) systems where
high speed, low power, and battery back up are
required.
The TC5563APL also features pin compatibility
with the 64k bit EPROM (TMM2764D). RAM and
EPROM are then interchangeable in the same
socket, resulting in flexibility in the definition of the
quantity of RAM versus EPROM in microprocessor
application systems.
The TC5563APL is offered in a dual-in-line 28 pin
0.3 inch width plastic package.
FEATURES
• Low Power Dissipation
27. 5mW/MHz (MAx.) Operating
• Standby Current: lJ1.A (Max.) Ta=25°C
• Access Time
TC5563APL-l0L: lOOns (Max.)
TC5563APL-12L: 120ns (Max.)
TC5563APL-15L: 150ns (Max.)
• 5V Single Power Supply
• Power Down Features: CE2, CE 1
• Fully Static Operation
at Data Retention Supply Voltage: 2.0 - 5. 5V
• Directly TIL Compatible
: All Inputs and Outputs
• Pin Compatible with 2764 type EPROM
• TC5565APL Family (Package Type)
PIN CONNECTION (TOP VIEW)
TC5563APL
64k bit EPROM
TMM2764D
A5
A2
AO
1/01
1/02
1/03
aND
28 VDD
Z7 R/N
26 CE2
25 A8
24 A9
23 All
22 ITE
21 AlO
20 CEI
19 1/0s
IS 1/07
17 1/06
16 I/Ob
Ib 1/04
VPP
A12
A3
A2
Al
AO
00
01
02
aND
VCC
PaM
N,C,
AS
A9
All
DE
AIO
IT
PIN NAMES
Ao-A,2
R/W
OE
CE" CE2
1/0,-1/08
Voo
GND
N. C.
Address Inputs
Read/Write Control Input
Output Enable Input
Chip Enable Inputs
Data Input/Output
Power (+5V)
Ground
No Connection
Package Type
Device Name
600 mil DIP
·TC5565APL
300 mil DIP
(Slim Package)
TC5563APL
Flat Package(SOP)
·TC5565AFL.
* : See TC5565APL/AFL Technical Date.
· BLOCK DIAGRAM.
- 1:3-55 -

1 page




TC5563APL-12L pdf
TIMING WAVEFORMS
o READ CYCLE (1)
ADDRESSES
TC5563APL-10L, TC5563APL-12L
TC5563APL-15L
tRC
OE
DOUT
OUTPUT
• WRITE CYCLE 1 (4) (R/W Controlled Write)
ADDRESSES
R/W
twc
twp
VIH -
VIL --~~~LLLLLLLL~U
tcw
tcw
tWR
DOUT
VIH -
VIL _ _ _ _ _ _ _ _ _ _ _ _ _- - '
tDS
DATA IN
STABLE
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