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PDF TC514256Z-85 Data sheet ( Hoja de datos )
| Número de pieza | TC514256Z-85 | |
| Descripción | DRAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TC514256Z-85 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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TOSHIBA MOS MEMORY PRODUCT
262,144 WORDS X 4 BIT DYNAMIC RAM
SI LICON GATE CMOS
DESCRIPTION
TC514256P/J/Z-85, TC514256P/J/Z-l0
TC514256P/J/Z-12
The TCs142s6P/J/Z is the new generation dynamic RAM organized 262,144 words by 4
bit. The TCs142s6P/J/Z utilizes TOSHIBA's CMOS Silicon gate process technology as well
as advanced circuit techniques to provide wide operating margins, both internally and to
the system user. Multiplexed address inputs permit the TCs142s6P/J/Z to be packaged in a
standard 20 pin plastic DIP and 26/20 pin plastic SOJ and 20/19 pin plastic ZIP. The
package size provides high system bit densities and is compatible with widely available
automated testing and insertion equipment. System oriented features include single power
supply of 5V±10% tolerance, direct interfacing capability with high performance logic
families such as Schottky TTL.
FEATURES
• 262,144 words by 4 bit organization
• Fast access time and cycle time
TC5l42s6P/J/Z-Bs-lO-12
tRAC R:AS Access Time
B5ns lOOns l20ns
tAA
Column Address
Access Time
45n9 SOns 60ns
tCAC CAS Access Time
30ns 30ns 35ns
tRC Cycle Time
l65ns 190ns 220ns
tpc Fast Page Mode
Cycle Time
SOns ssns 70ns
• Single power supply of sV±lO% with a built-
in VBB generator
PIN CONNECTION (TOP VIEW)
Plastic DIP
VOL
1/02
WRIH
iUJJ
N.C.
AO
Al
A2
A3
1
VCC
Oi
A8
A7
AIS
Mi
A'
Plastic SOJ
(/0 1 1
1/02 2
WRITE 3
HAS ,
N.C. 0
AO
Al
A2
A3
vcc
Plastic ZIP
PIN NAr·1ES
AO"'A8
m
Address Inputs
Row Address Strobe
~ Column Address Strobe
WRITE Read/Write Input
DE Output Enable
1/01'" 1/04 Data Input/Output
Vce Power (+5V)
VSS Ground
N.C. No Connection
• Low Power
4l3mW MAX. Operating(TCs14256P/J/Z-Bs)
3sBmW MAX. Operating(TCs142s6P/J/Z-lO)
303mW MAX. Operating(TCs142s6P/J/Z-12)
s.smW MAX. Standby
• Output unlatched at cycle end allows
two-dimensional chip selection
• Read-Modify-Write, CAS before RAS
refresh, RAS-only refresh, Hidden
refresh, and Fast P~ge Mode capability
• All inputs and outputs TTL compatible
• 512 refresh cycles/Bms
• Package Plastic DIP: TCs142s6P
Plastic SOJ: TCs14256J
Plastic ZIP: TCs14256Z
BLOCK DIAGRAr-1
VOl V02 V03 I/O'
AO
Al
A2
A3
A'
AO
AIS
A7
A8
':T;aG'fRATS 3.A;:;
~ENERATOR
- A-141 -
1 page  
TC514256P/ J/Z-85, TC514256P/ J/Z-l 0
TC514256P/J/Z-12
NOTES:
1. Stresses greater than those listed under "Absolute Maximum Ratings" May cause
permanent damage to the device.
2. All voltage are reference to VSS.
3. Iccl, Icc3, Icc4, Icc6 depend on cycle rate.
4. Iccl, Icc4 depend on output loading. Specified value are obtained with the output
open.
5. An initial pause of 20~s is required after power-up followed by 8 RAS cycles
before proper device operation is achieved. In case of using internal refresh
counter, a minimum of 8 CAS Before ~ initialization cycles instead of 8 RAS
cycles are required.
6. AC measurements assume tT=5ns.
7. VIR(min.) and VIL(max.) are reference levels for measuring timing of input signals.
Also. transition times are measured between VIR and VIL.
8. Measurement with a load equ1valent to 2 TTL loads and lOOpF.
9. tOFF(max.) and tOEZ(max.) define .the time at which the output achieves the open
circuit condition and is not referenced to output voltage levels.
10. Either tRCH or tRRH must be satisfied for a read cycle.
11. These parameters are referenced to CAS leading edge in early write cycles and to
WRITE leading edge in read-modify-write cycles.
12. twcs, tRWD, tCWD and tAWD are not restrictive operating parameters. They are
included the data sheet as electrical characteristics only. If twcs~tWr.~(min.)
the cycle is an early write cycle and data out pin will remain open cirCUit (high
impedance) through the entire cycle; If tRWD~tRWD(min.), tCWD~tCWD(min.) and
tAWD~tAWD(min.), the cycle is a read-modify-write cycle and data out will contain
data read from the selected cell: If neither of the above sets of conditions is
satisfied, the condition of the data out (at access time) is indeterminate.
13. Operation within the tRCO(max.) limit insures that tRAC(max.) can be met.
tRCO(max.) is specified as a reference point only: If tRCO is greater than the
specified tRCO(max.) limit, then access time is controlled by tCAC.
14. Operation within the tRAo(max.) limit insures that tRAc(max.) can be met.
tRAO(max.) is specified as a reference point only: If tRAD is greater than the
specified tRAD(max.) limit, then access time is controlled by tAA.
I
-A-145 -
5 Page 
HIDDEN REFRESH CYCLE (READ)
V1H---~
VIL-
TC514256PIJ/Z-85, TC514256PIJ/Z-l 0
TC514256P/J/Z-12
..
t
tCRP
AO-AB
V1H _~~~~~~L-~------1~~~~~~~~~~rn~~~~~Tn~
VIL-""'-'.J..I..~..J.../...<~
VIH _ ..,...,..,...,....,.~~r""I'""'l".,..,...,...,....,..,...
V1L -~.J..I..~~~~~~~~---____-
_ _ _ _~+U~~.J..I..~.J..I..""'-'~~~~
VOH -
I/01-1/04.
---------{I!
VOL -
VALID DATA-OUT
~ :"H"or"L"
-A-151 -
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet TC514256Z-85.PDF ] | |
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