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PDF TC51832P-12 Data sheet ( Hoja de datos )
| Número de pieza | TC51832P-12 | |
| Descripción | CMOS Pseudo Static RAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA MUS MEMORY PRODUClI
32,768 WORD X 8 CMOS PSEUDO STATIC RAM
SILICON MONOLITHIC
SILICON GATE CMOS
TC51832P-85, TC51832P-l0
TC51832P-12
IOEseRI PrIm! I
The TCSl832P is a 2S6K bit high speed cnos pseudo static RAH organized as 32,768
Hords by 8 bits. The TCSl832P utilized one transistor dynamic memory cell ~vith C~IOS
peripheral circuit to provide large capacity, high speed and low power features. System
oriented features include single pot"er supply of SV±lO% torelance. The OE/RFSH input
allotvs t~1I'O types of refresh operation - auto refresh .:lnd self refresh. The TCSl832P
also features static RA1-1 like ~.,rrite function that the input data is ~.Jritten into the
~emory cell at the rising edge of R/W, thus being easy to interface with microprocessor.
The TCSI832P is a pin-compatible tvith 256K bit GIOS static RA~'I - TCS52S7P and is
r.;ouided .J. standard 0.6 inch ~Jid th plas tic DIP.
IFEATURESI
-- -• Organization: 32,768 \·:ord x 3 bit
• Fast Access Time and Cycle Time
TC51832P-85
TC51832P-IO
tCEA CE Access Time . G5ns
lOOns
tOEA OE Access Time 35ns
40ns
t1C Cycle Time
USns
160ns
TC51832P-12
120ns
SOns
I90ns
• Single Power Supply: SV~lO%
• Static RA1·! like ~irite Function
• All inputs and outputs: TTL Compatible
IIPHI COnNECTION
(TOP V[f0N)
• Low Power Dissipation
Operating
303~J(TC51332P-85)
248mW(TCSI832P-IO)
220mhl (TC518 32P-12)
Standby
5.5mH
Self Refresh: 5.SmW
• THO types of Refresh Cperation
Cilpability
Auto Refresh
Self Refresh
• Pin Compatible with 256K bit aIDS
Static RAH TC552S7P
Al4
Al2
A7
A6
A5
A4
A3
A2
Al
AO
I/O I
I/O 2
I/03
GND
VDD
R/W
Al3
A8
A9
All
OE/RFSH
AIO
CE
I/08
I/07
I/06
I/05
I/04
IBLOCK OIAGRMII
VDD GND
. Al4-A8
COLUMN
DECODER
iPIIl rlAr'IEsl
AO 'V Al4
R/~~
Address Inputs
Read/Hrite Control
Input
OE/RFSH
Output Enable/Refresh
Input
CE Chip Enable Input
II/ol 'V 1/08 Data Input/Output
VDD Power (+5V)
GND Ground
A7-AO
R/W o---~~-t--------------------------------~
- 8-107-
00
;0::::r
~
;0::::r
1 page  
TC51832P-85, TC51832P-l0
TC51832P-12
CAPACITANCE (VOO=5V±10%, f=Umz, Ta=O '" 70°C)
SYNBOL
PARM·fETER
CII Input Capacitance (AO '" A14)
CI2 Input Capacitance (CE, OE/RFSH, R/m
CIO Input/Output Capacitance (I/Ol'" 1/08)
HI~. HAX. UNIT
- 5 pF
- 7 pF
- 7 pF
~OTES:
1) Stresses greater than those listed under "Absolute Haximum Ratings" may cause
permanent damage to the device.
2) All voltages are reference to G~O.
3) 1000 depend on cycle rate.
4) 1000 depend on output loading. Specified value are obtained with the output open.
5) An initial pause 0 f lms ~vith high CE and high OE/RFSH is required after pO\Ver-up
before proper device operation is achieved.
6) AC measurements assume t r =5ns.
7) VIH(min.) and VIL(max.) are reference levels for measuring timing of input sig-
nals. Also, transition times are measured between VIH and VIL.
8) Measured with a load equivalent to 2 TTL loads and 100pF.
9) The OE/RFSH input operates as the output enable input(OE) and refresh control
input(RFSH) under the condition of that CE=VIL and CE=VIH, respectively.
10) tCHZ, tOHZ, tt.JHZ define the time at \vhich the output achieves the ope~ circuit
condition and is not reference to output voltage levels.
11) In tvrite cycles, the input data is latched at the earlier of R/~.J or CE rising
edge. Therefore the input data must be valid during set-~p time(tDS~' tOSC)
and hold time(tDHW, tOHC).
12) All address are latched at the falling edge of CEo Therefore must be valid
during tASC and tARC.
13) Two refres6 operation - auto refresh and self refresh are determind by the
OE/RFSH pulse tvidth under the condition of CE=VIH.
Auto refresh: OE/RFSH pulse tvidth ~ tFAP(max.)
Self refresh: OE/RFSH pulse width ~ tFAS (min.)
The following timing parameter must be kept before device proper operation is
achieved after refresh.
Auto refresh: tFCE and tFSR
Self refresh: tFRS
- 8-111 -
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet TC51832P-12.PDF ] | |
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