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PDF FCH077N65F_F085 Datasheet ( Hoja de datos )

Número de pieza FCH077N65F_F085
Descripción MOSFET
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo

Total 9 Páginas
		
FCH077N65F_F085 Hoja de datos, Descripción, Manual
FCH077N65F_F085
December
2014
N-Channel SuperFET II FRFET MOSFET
650 V, 54 A, 77 mΩ
Features
„ Typical RDS(on) = 68 mΩ at VGS = 10 V, ID = 27 A
„ Typical Qg(tot) = 126 nC at VGS = 10V, ID = 27 A
„ UIS Capability
„ Qualified to AEC Q101
„ RoHS Compliant
Description
G
D
S
D
G
TO-247
S
SuperFET® II MOSFET is Fairchild Semiconductor’s brand-new
high voltage super-junction (SJ) MOSFET family that is utilizing
charge balance technology for outstanding low on-resistance
and lower gate charge performance. This technology is tailored
to minimize conduction loss, provide superior switching
performance, dv/dt rate and higher avalanche energy.
Consequently SuperFETII is very well suited for the Soft switching
and Hard Switching topologies like High Voltage Full Bridge and
Half Bridge DC-DC, Interleaved Boost PFC, Boost PFC for HEV-EV
automotive.
SuperFET II FRFET® MOSFET’s optimized body diode reverse
recovery performance can remove additional component and
improve system reliability.
For current package drawing, please refer to the Fairchild web
site  at  https://www.fairchildsemi.com/packagedrawings/TO/
TO247A03.pdf
Application
„ Automotive On Board Charger
„ Automotive DC/DC converter for HEV
Maximum Ratings TC = 25°C unless otherwise noted
Symbol
Parameter
VDSS
VGS
ID
Drain to Source Voltage
Gate to Source Voltage
Drain Current - Continuous (VGS=10) (Note 1)
Pulsed Drain Current
EAS
dv/dt
Single Pulse Avalanche Rating
MOSFET dv/dt
Peak Diode Recovery dv/dt
(Note 2)
(Note 3)
PD
Power Dissipation
Derate Above 25oC
TJ, TSTG
RθJC
RθJA
Operating and Storage Temperature
Maximum Thermal Resistance Junction to Case
Maximum Thermal Resistance Junction to Ambient
(Note 4)
Ratings
650
±20
54
See Fig 4
1128
100
50
481
3.85
-55 to + 150
0.26
40
Units
V
V
A
A
mJ
V/ns
W
W/oC
oC
oC/W
oC/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FCH077N65F FCH077N65F_F085
TO-247
-
-
30
Notes:
1: Current is limited by bondwire configuration.
2: Starting TJ = 25°C, L = 18.65mH, IAS = 11A, VDD = 100V during inductor charging and VDD = 0V during time in avalanche.
3: ISD 27A, di/dt 200 A/us, VDD 380V, starting TJ = 25°C.
4: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder
mounting surface
presented here is
of the
based
drain pins. RθJC is
on mounting on a 1
guaranteed by design,
in2 pad of 2oz copper.
while
RθJAis
determined
by
the
board
design.
The maximum rating
©2014 Fairchild Semiconductor Corporation
FCH077N65F_F085 Rev. B1
1
www.fairchildsemi.com

1 page

FCH077N65F_F085 pdf
Typical Characteristics
3.0
PULSE DURATION = 80μs
2.5 DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
0.5
0.0
-80
ID = 27A
VGS = 10V
-40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE(oC)
Figure 11. Normalized RDSON vs. Junction
Temperature
1.2
VGS = VDS
1.1 ID = 250μA
1.0
0.9
0.8
0.7
0.6
0.5
-80
-40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE(oC)
Figure 12. Normalized Gate Threshold Voltage vs.
Temperature
1.15
1.10
ID = 10mA
1.05
1.00
0.95
0.90
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 13. Normalized Drain to Source
Breakdown Voltage vs. Junction Temperature
10
ID = 27A
8
6
VDS = 260V
VDS = 325V
VDS = 390V
4
2
0
0 20 40 60 80 100 120 140
Qg, GATE CHARGE(nC)
Figure 15. Gate Charge vs. Gate to Source
Voltage
100000
10000
Ciss
1000
100
Coss
10
f = 1MHz
VGS = 0V
Crss
1
0.1 1 10 100 1000
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 14. Capacitance vs. Drain to Source
Voltage
30 Figure 16.
24
18
12
6
0
0 130 260 390 520
VDS, Drain to Source Voltage [V]
Figure 16. Eoss vs. Drain to Source
Voltage
650
FCH077N65F_F085 Rev. B1
5
www.fairchildsemi.com

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