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PDF TC511000J-12 Data sheet ( Hoja de datos )

Número de pieza TC511000J-12
Descripción DRAM
Fabricantes Toshiba 
Logotipo Toshiba Logotipo



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No Preview Available ! TC511000J-12 Hoja de datos, Descripción, Manual

TOSHIBA MOS MEMORY PRODUCT
1,048,576 WORDS X 1 BIT DYNAMIC RAM
SILICON GATE CMOS
DESCRIPTION
TC511000P/J/Z-85, TC511000P/J/Z-l0
TC511000P/J/Z-12
The TC5llOOOP/J/Z is the ne~v generation dynamic RAN organized 1,048,576 words by 1 bit.
The TC5llOOOP/J/Z utilizes TOSHIBA's CHOS Silicon gate process technology as well as ad-
vanced circuit techniques to provide wide operating margins, both internally and to the
system user. Multiplexed address inputs permit the TC5llOOOP/J/Z to be packaged in a
standard 18 pin plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic ZIP. The package
size provides high system bit densities and is compatible with widely available automated
testing and insertion equipment. System oriented features include single power supply of
5V±10% tolerance" direct interfacing capability with high performance logic families such
as Schottky TTL. IJTest Mode" function is implemented from Ilevision C.
FEATURES
• 1,048,576 words by 1 bit organization
• Fast access time and cycle time
TC5llOOOP/J/Z-85-10-l2
tRAC HAS Access Time
tM
Column Address
Access Time
85ns
45ns
lOOns l20ns
Sans 60ns
tCAC CAS Access Time
t RC Cycle Time
tpc
Fast Page Hade
Cycle Time
25ns
l65ns
SOns
25ns 30ns
190ns 220ns
55ns 70ns
• Single pOvler supply of 5V±10% ~vith a built-
in VEE generator
PIN COmlE:TICN (TOP VIEt-l)
• Low Power
3n5m~J HAX. Operating (TC5ll000P / J /Z-85)
330mtoJ UP.X. Operating(TC5ll000P/J/Z-10)
275mW MAX. Operating(TC5ll000P/J/Z-12)
5.5mtJ HA.,{. Standby
• Output unlatched at cycle end allows
tHo-dimensional chip selection
• Common I/O capability using "EARLY WRITE"
operation
• Read-Modify-Hrite, CAS before HAS refrl::'~~'J I
RAS-only refresh, Hidden refresh, Fast
Page Mode and Test Mode capability
• All inputs and output TTL compatible
• 512 refresh cycles/8ms
• Package Plastic DIP: TC5ll000P
Plastic SOJ: TC5ll000J
Plastic ZIP: TC5ll000Z
Plastic DIP
Plastic SOJ Plastic ZIP
DIU
~
ID:S
11"
AO
1
A2
A3
Vss
DOU1
~
A9
A8
A7
All
A5
a4.
~
roili
TF
N.C.
AO
Al
A2
A3
VCC
PHI rlN·1ES
AD '" A9
m
DIN
DOUT
CAS
WRITE
Vec
VSS
TF
N.C.
Address Inputs
Row Address Strobe
Data In
Data Out
Column Address Strobe
Read/Write Input
Power (+5V)
Ground
Test Function
No Connection
Vss
~1
N.C.
A9
A8
A7
A6
A5
A4.
BLOCK DIAGRAf.1
Al
A3 AO
M, Al
AS A2
A8 A3
A4.
AS
AS
A7
AS
A9
GUDGTRATE DIAG -Q Vee
L-0_E_N_E_RA_T_O_R_ - - - ' --0 V S8
- A-85 -

1 page




TC511000J-12 pdf
TC511000P/J/Z-85, TC511000P/J/Z-l0
TC511000P/J/Z-12
CAPACITANCE (VCC=SV±lO%, f=IMHz, Ta=O IV 70°C)
SYMBOL
CII
CI2
Co
PARAMETER
Input Capacitance (AO IV A9, DIN)
Input Capacitance (RAS, CAS, ,~VRITE IT)
Output Capacitance (DOUT)
MIN. MAX. UNIT
-5
- 7 pF
- 7 .-
NOTES:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device.
2. All Voltages are referenced to VSS.
3. ICCI, ICC3, ICC4, ICC6 depend on cycle rate.
4. ICCI' ICC4 depend on output loading. Specified values are obtained with the
output open.
S. An initial pause of 200~s is required after power-up followed by 8 RAS cycles
before proper device operation is achieved. In case of using internal refresh
counter, a minimum of 8 CAS before RAS initialization cycles instead of 8 RAS
cycles are required.
6. AC measurements assume tT=5ns.
7. VIR(min.) and VIL(max.) are reference levels for measuring timing of input
signals. Also', transition times are measured between VIR and VIL.
8. Measured with a load equivalent to 2 TTL loads and 100pF.
9. tOFF(max.) defines the time at which the output achieves the open circuit
condition and is not referenced to output voltage levels.
10. Either tRCR or tRRH must be satisfied for a read cycle.
11. These parameters are referenced to CAS leading edge in early write cycles and
to WRITE leading edge in read-write cycles.
12. t~vCS' tRWU, tcwn and tAWO are not restrictive operating parameters. They are
included the data sheet as electrical characteristics only. If twcs ~ twcs
(min.), the cycle is an early write cycle and data out pin will remain open
circuit (high impedance) through the entire cycle; If tRWO ~ truiD(min.),
tCWD ~ tcWO(min.) and tAvID f tAWD(min.), the cycle is a read-write cycle and
data out will contain data read from the selected cell: If neither of the
above sets of conditions is satisfied, the condition of the data out (at
access time) is indeterminate.
13. Operation within the tRco(max.) limit insures that tRAC(max.) can be met.
tRCD(max.) is specified as a reference point only: If tRCD is greater than the
specified tRco(max.) limit, then access time is controlled by tCAC.
14. Operation within the tRAD(max.) limit insures that tRAC(max.) can be met.
tRAD(max.) is specified as a reference point only: If tRAO is greater then the
specified tRAD(max.) limit, then access time is controlled by tAA.
- A-89 -

5 Page





TC511000J-12 arduino
FAST PAGE MODE READ-t.ffiITE CYCLE
TC511000P/ J/Z-85, TC511 OOOP/ J/Z-l 0
TC511000P/J/Z-12
VIL -
VIH - ----=X=---t-+----~
AO-A9 vIH-
VIL -
__ VIH-
WRITE
VIH -
'=RAC
VOH -
---------~[V
VOL -
~: "H'lor"L'1
NOTE: "TF" pin should be connected to VIL level or open, if "Test
Mode" is not used.
- A-95 -

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