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PDF ICS843S104I-133 Data sheet ( Hoja de datos )
| Número de pieza | ICS843S104I-133 | |
| Descripción | Crystal-to-LVPECL 133MHz Clock Synthesizer | |
| Fabricantes | IDT | |
| Logotipo |  |
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Crystal-to-LVPECL 133MHz
Clock Synthesizer
ICS843S104I-133
DATA SHEET
General Description
The ICS843S104I-133 is a PLL-based clock
ICS synthesizer specifically designed for low phase noise
HiPerClockS™ applications. This device generates a 133.33MHz
differential LVPECL clock from an input reference of
25MHz. The input reference may be derived from an
external source or by the addition of a 25MHz crystal to the on-chip
crystal oscillator. An external reference is applied to the PCLK,
nPCLK pins.The device offers spread spectrum clock output for
reduced EMI applications. An I2C bus interface is used to enable or
disable spread spectrum operation as well as to select either a down
spread value of -0.35% or -0.5%.The ICS843S104I-133 is available
in a lead-free 32-Lead VFQFN package.
Features
• Four LVPECL output pairs
• Crystal oscillator interface: 25MHz
• Differential PCLK/nPCLK input pair
• PCLK/nPCLK supports the following input types: LVPECL, CML,
SSTL
• Output frequency: 133.33MHz
• PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant
• RMS phase jitter @ 133.33MHz (12kHz – 20MHz):
1.2ps (typical)
• I2C support with readback capabilities up to 400kHz
• Spread Spectrum for electromagnetic interference (EMI) reduction
• 3.3V operating supply mode
• -40°C to 85°C ambient operating temperature
• Available lead-free (RoHS 6) package
Block Diagram
REF_SEL Pulldown
PCLK Pulldown
nPCLK Pullup/Pulldown
25MHz
XTAL_IN
OSC
XTAL_OUT
SDATA Pullup
SCLK Pullup
1
PLL
0
I2C
Logic
4
Q[1:4]
4
nQ[1:4]
Pin Assignment
32 31 30 29 28 27 26 25
VCC 1
24 VEE
REF_SEL 2
23 nQ3
VEE 3
22 Q3
PCLK 4
21 VCC
nPCLK 5
20 VEE
VEE 6
19 nQ4
VCCA 7
18 Q4
VEE 8
17 VCC
9 10 11 12 13 14 15 16
ICS843S104I-133
32-Lead VFQFN
5.0mm x 5.0mm x 0.925mm
package body
K Package
Top View
ICS843S104BKI-133 REVISION A JUNE 9, 2009
1
©2009 Integrated Device Technology, Inc.
1 page  
ICS843S104I-133 Data Sheet
CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER
Control Registers
Table 3D. Byte 0: Control Register 0
Bit @Powerup
Name Description
7 0 Reserved Reserved
61
Q4EN
Q4, nQ4 Output Enable
0 = Low
1 = Enable
51
Q3EN
Q3, nQ3 Output Enable
0 = Low1 = Enable
41
Q2EN
Q2, nQ2 Output Enable
0 = Low
1 = Enable
31
Q1EN
Q1, nQ1 Output Enable
0 = Low
1 = Enable
2 1 Reserved Reserved
1 0 Reserved Reserved
0 0 Reserved Reserved
Table 3E. Byte 1: Control Register 1
Bit @Powerup Name
Description
7
0
Reserved
Reserved
6
0
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
Table 3F. Byte 2: Control Register 2
Bit @Powerup Name Description
7
1
SS_SEL
Spread Spectrum Selection
0 = -0.35%, 1 = - 0.5%
6 1 Reserved Reserved
5 1 Reserved Reserved
4 0 Reserved Reserved
3 1 Reserved Reserved
Q Spread Spectrum Enable
2 0 SSM 0 = Spread Off,
1 = Spread On
1 1 Reserved Reserved
0 0 Reserved Reserved
Table 3G. Byte 3:Control Register 3
Bit @Powerup
Name
7 1 Reserved
6 0 Reserved
5 1 Reserved
4 0 Reserved
3 1 Reserved
2 1 Reserved
1 1 Reserved
0 1 Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 3H. Byte 4: Control Register 4
Bit @Powerup
Name
7 0 Reserved
6 0 Reserved
5 0 Reserved
4 0 Reserved
3 0 Reserved
2 0 Reserved
1 0 Reserved
0 1 Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 3I. Byte 5: Control Register 5
Bit @Powerup
Name
7 0 Reserved
6 0 Reserved
5 0 Reserved
4 0 Reserved
3 0 Reserved
2 0 Reserved
1 0 Reserved
0 0 Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ICS843S104BKI-133 REVISION A JUNE 9, 2009
5
©2009 Integrated Device Technology, Inc.
5 Page 
ICS843S104I-133 Data Sheet
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS843S104I-133 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VCC ,VCC_XOSC and VCCA should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VCC pin and also shows that VCCA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the VCCA pin.
CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER
VCC
VCCA
3.3V
.01µF
10Ω
10Ω
.01µF 10µF
VCC_XOSC
.01µF 10µF
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
All control pins have internal pullup and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
PCLK/nPCLK Inputs
For applications not requiring the use of a differential input, both the
PCLK and nPCLK pins can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from PCLK to
ground.
ICS843S104BKI-133 REVISION A JUNE 9, 2009
11
©2009 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ICS843S104I-133.PDF ] | |
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