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PDF 813N252DI-02 Data sheet ( Hoja de datos )
| Número de pieza | 813N252DI-02 | |
| Descripción | Jitter Attenuator & FemtoClock NG Multiplier | |
| Fabricantes | IDT | |
| Logotipo |  |
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Jitter Attenuator & FemtoClock NG®
Multiplier
813N252DI-02
DATA SHEET
General Description
Features
The 813N252DI-02 device uses IDT's fourth generation
FemtoClock® NG technology for optimal high clock frequency and
low phase noise performance, combined with a low power
consumption and high power supply noise rejection. The
813N252DI-02 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation and
frequency translation.
The813N252DI-02 is a fully integrated Phase Locked loop utilizing a
FemtoClock NG Digital VCXO that provides the low jitter, high
frequency SONET/PDH output clock that easily meets OC-48 jitter
requirements. This VCXO technology simplifies PLL design by
replacing the pullable crystal requirement of analog VCXOs with a
fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is
provided by an external loop filter. Pre-divider and output divider
multiplication ratios are selected using device selection control pins.
The multiplication ratios are optimized to support most common
clock rates used in PDH, SONET and Ethernet applications. The
device requires the use of an external, inexpensive fundamental
mode 27MHz crystal. The device is packaged in a space-saving
32-VFQFN package and supports industrial temperature range.
Pin Assignment
LF1
32 31 30 29 28 27 26 25
1 24
• Fourth generation FemtoClock® NG technology
• Two LVPECL output pairs
• Each output supports independent frequency selection at 25MHz,
125MHz, 156.25MHz and 312.5MHz
• Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, HCSL
• Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
• Crystal interface optimized for a 27MHz, 10pF parallel resonant
crystal
• Attenuates the phase jitter of the input clock by using a low-cost
fundamental mode crystal
• Customized settings for jitter attenuation and reference tracking
using an external loop filter connection
• FemtoClock NG frequency multiplier provides low jitter, high
frequency output
• Absolute pull range: ±100ppm
• Power supply noise rejection (PSNR): -85dB (typical)
• FemtoClock NG VCXO frequency: 2500MHz
• RMS phase jitter @ 156.25MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.6ps (typical)
• RMS phase jitter @ 125MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.65ps (typical)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
VEE
LF0 2
23 nQB
ISET 3
22 QB
VEE
CLK_SEL
4
5
813N252DI-02
21 VCCO
20 nQA
VCC
RESERVED
VEE
6
7
8
9
19
18
17
10 11 12 13 14 15 16
QA
VEE
ODASEL_0
32-pin, 5mm x 5mm VFQFN Package
REVISION 1 08/14/15
1
©2015 INTEGRATED DEVICE TECHNOLOGY, INC.
1 page  
813N252DI-02 DATA SHEET
Table 3C. Frequency Function Table
Input Frequency (MHz)
0.008
0.008
0.008
0.008
1.544
1.544
1.544
1.544
2.048
2.048
2.048
2.048
19.44
19.44
19.44
19.44
25
25
25
25
77.76
77.76
77.76
77.76
125
125
125
125
155.52
155.52
155.52
155.52
NOTE: x denotes A or B.
÷P Value
1
1
1
1
193
193
193
193
256
256
256
256
1944
1944
1944
1944
2500
2500
2500
2500
7776
7776
7776
7776
12500
12500
12500
12500
15552
15552
15552
15552
FemtoClock NG VCXO Center
Frequency (MHz)
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
÷Nx Value
100
20
16
8
100
20
16
8
100
20
16
8
100
20
16
8
100
20
16
8
100
20
16
8
100
20
16
8
100
20
16
8
Output Frequency (MHz)
25
125
156.25
312.5
25
125
156.25
312.5
25
125
156.25
312.5
25
125
156.25
312.5
25
125
156.25
312.5
25
125
156.25
312.5
25
125
156.25
312.5
25
125
156.25
312.5
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
5
REVISION 1 08/14/15
5 Page 
813N252DI-02 DATA SHEET
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock is driven from a single-ended 2.5V
LVCMOS driver and the DC offset (or swing center) of this signal is
1.25V, the R1 and R2 values should be adjusted to set the V1 at
1.25V. The values below are for when both the single ended swing
and VCC are at the same voltage. This configuration requires that the
sum of the output impedance of the driver (Ro) and the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the input will attenuate the signal in half. This
can be done in one of two ways. First, R3 and R4 in parallel should
equal the transmission line impedance. For most 50 applications,
R3 and R4 can be 100. The values of the resistors can be increased
to reduce the loading for slower and weaker LVCMOS driver. When
using single-ended signaling, the noise rejection benefits of
differential signaling are reduced. Even though the differential input
can handle full rail LVCMOS signaling, it is recommended that the
amplitude be reduced while maintaining an edge rate faster than
1V/ns. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
11
REVISION 1 08/14/15
11 Page | ||
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