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PDF CD4047BC Data sheet ( Hoja de datos )
| Número de pieza | CD4047BC | |
| Descripción | Low Power Monostable/Astable Multivibrator | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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October 1987
Revised March 2002
CD4047BC
Low Power Monostable/Astable Multivibrator
General Description
The CD4047B is capable of operating in either the
monostable or astable mode. It requires an external capac-
itor (between pins 1 and 3) and an external resistor
(between pins 2 and 3) to determine the output pulse width
in the monostable mode, and the output frequency in the
astable mode.
Astable operation is enabled by a high level on the astable
input or low level on the astable input. The output fre-
quency (at 50% duty cycle) at Q and Q outputs is deter-
mined by the timing components. A frequency twice that of
Q is available at the Oscillator Output; a 50% duty cycle is
not guaranteed.
Monostable operation is obtained when the device is trig-
gered by LOW-to-HIGH transition at + trigger input or
HIGH-to-LOW transition at − trigger input. The device can
be retriggered by applying a simultaneous LOW-to-HIGH
transition to both the + trigger and retrigger inputs.
A high level on Reset input resets the outputs Q to LOW, Q
to HIGH.
Features
s Wide supply voltage range: 3.0V to 15V
s High noise immunity: 0.45 VDD (typ.)
s Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
Special Features
s Low power consumption: special CMOS oscillator
configuration
s Monostable (one-shot) or astable (free-running)
operation
s True and complemented buffered outputs
s Only one external R and C required
Monostable Multivibrator
Features
s Positive- or negative-edge trigger
s Output pulse width independent of trigger pulse duration
s Retriggerable option for pulse width expansion
s Long pulse widths possible using small RC components
by means of external counter provision
s Fast recovery time essentially independent of pulse
width
s Pulse-width accuracy maintained at duty cycles
approaching 100%
Astable Multivibrator Features
s Free-running or gatable operating modes
s 50% duty cycle
s Oscillator output available
s Good astable frequency stability
typical= ±2% + 0.03%/°C @ 100 kHz
frequency= ±0.5% + 0.015%/°C @ 10 kHz
deviation (circuits trimmed to frequency VDD = 10V
±10%)
Applications
• Frequency discriminators
• Timing circuits
• Time-delay applications
• Envelope detection
• Frequency multiplication
• Frequency division
Ordering Code:
Order Number Package Number
Package Description
CD4047BCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4047BCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation DS005969
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 5)
TA = 25°C, CL = 50 pF, RL = 200k, input tr = tf = 20 ns, unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ
tPHL, tPLH
Propagation Delay Time Astable,
Astable to Osc Out
VDD = 5V
VDD = 10V
VDD = 15V
200
100
80
tPHL, tPLH
Astable, Astable to Q, Q
VDD = 5V
VDD = 10V
VDD = 15V
550
250
200
tPHL, tPLH
+ Trigger, − Trigger to Q
VDD = 5V
VDD = 10V
VDD = 15V
700
300
240
tPHL, tPLH
+ Trigger, Retrigger to Q
VDD = 5V
VDD = 10V
VDD = 15V
300
175
150
tPHL, tPLH
Reset to Q, Q
VDD = 5V
VDD = 10V
VDD = 15V
300
125
100
tTHL, tTLH
Transition Time Q, Q, Osc Out
VDD = 5V
VDD = 10V
VDD = 15V
tWL, tWH
Minimum Input Pulse Duration
Any Input
VDD = 5V
VDD = 10V
VDD = 15V
tRCL, tFCL
+ Trigger, Retrigger, Rise and
VDD = 5V
Fall Time
VDD = 10V
VDD = 15V
CIN
Average Input Capacitance
Any Input
Note 5: AC Parameters are guaranteed by DC correlated testing.
100
50
40
500
200
160
5
Max
400
200
160
900
500
400
1200
600
480
600
300
250
600
250
200
200
100
80
1000
400
320
15
5
5
7.5
Units
ns
ns
ns
ns
ns
ns
ns
µs
pF
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CD4047BC.PDF ] | |
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