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PDF FDD5N50NZ Data sheet ( Hoja de datos )
| Número de pieza | FDD5N50NZ | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FDD5N50NZ
N-Channel UniFETTM II MOSFET
500 V, 4 A, 1.5 Ω
Features
• RDS(on) = 1.38 Ω (Typ.) @ VGS = 10 V, ID = 2 A
• Low Gate Charge (Typ. 9 nC)
• Low Crss (Typ. 4 pF)
• 100% Avalanche Tested
• Improved dv/dt Capability
• ESD Imoroved Capability
• RoHS Compliant
Applications
• LCD/LED/PDP TV
• Lighting
• Uninterruptible Power Supply
November 2013
Description
UniFETTM II MOSFET is Fairchild Semiconductor’s high voltage
MOSFET family based on advanced planar stripe and DMOS
technology. This advanced MOSFET family has the smallest
on-state resistance among the planar MOSFET, and also pro-
vides superior switching performance and higher avalanche
energy strength. In addition, internal gate-source ESD diode
allows UniFETTM II MOSFET to withstand over 2kV HBM surge
stress. This device family is suitable for switching power con-
verter applications such as power factor correction (PFC), flat
panel display (FPD) TV power, ATX and electronic lamp bal-
lasts.
D
G
S
D
D-PAK
G
S
Absolute Maximum Ratings TC = 25oC unless otherwise noted.
Symbol
VDSS
VGSS
ID
IDM
EAS
IAR
EAR
dv/dt
PD
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Drain Current
- Continuous (TC = 25oC)
- Continuous (TC = 100oC)
- Pulsed
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation
(TC = 25oC)
- Derate Above 25oC
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
TJ, TSTG
TL
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering, 1/8” from Case for 5 Seconds
Thermal Characteristics
Symbol
RθJC
RθJA
Parameter
Thermal Resistance, Junction to Case, Max.
Thermal Resistance, Junction to Ambient, Max.
FDD5N50NZTM
500
±25
4
2.4
16
304
4
6.2
10
62
0.5
-55 to +150
300
FDD5N50NZTM
2.0
90
Unit
V
V
A
A
mJ
A
mJ
V/ns
W
W/oC
oC
oC
Unit
oC/W
©2010 Fairchild Semiconductor Corporation
FDD5N50NZ Rev. C1
1
www.fairchildsemi.com
1 page  
IG = const.
Figure 12. Gate Charge Test Circuit & Waveform
V10GVS
VDS
VGS
RG
RL
VDD
VDS
90%
DUT
VGS 10%
td(on)
tr
t on
Figure 13. Resistive Switching Test Circuit & Waveforms
td(off)
tf
t off
VGS
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
©2010 Fairchild Semiconductor Corporation
FDD5N50NZ Rev. C1
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet FDD5N50NZ.PDF ] | |
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