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High Speed 12-Bit Monolithic D/A Converters - Analog Devices

Número de pieza AD565A
Descripción High Speed 12-Bit Monolithic D/A Converters
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo
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AD565A datasheet

1 Page

AD565A pdf
AD566A–SPECIFICATIONS(TA = 25؇C, VEE = –15 V, unless otherwise noted)
Parameter
AD566AJ
Min Typ
Max
AD566AK
Min Typ Max
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1”
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
Bit OFF Logic “0”
2.0 5.5
0 0.8
120 300
35 100
2.0
0
5.5
0.8
120 300
35 100
RESOLUTION
12 12
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar (Adjustable to Zero per Figure 3)
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed)
Capacitance
Compliance Voltage
TMIN to TMAX
ACCURACY (Error Relative to
Full Scale) 25°C
TMIN to TMAX
–1.6
؎0.8
6
–1.5
–2.0
± 1.0
8
0.01
0.05
25
± 1/4
(0.006)
± 1/2
(0.012)
–2.4
؎1.2
10
0.05
0.15
+10
؎1/2
(0.012)
؎3/4
(0.018)
–1.6
؎0.8
6
–1.5
–2.0
± 1.0
8
0.01
0.05
25
± 1/8
(0.003)
± 1/4
(0.006)
–2.4
؎1.2
10
0.05
0.1
+10
؎0.35
(0.0084)
؎1/2
(0.012)
DIFFERENTIAL NONLINEARITY
25°C
TMIN to TMAX
TEMPERATURE COEFFICIENTS
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
± 1/2 ؎3/4
± 1/4 ؎1/2
MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED
12
5 10
7 10
2
12
5 10
35
2
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
250 350
250 350
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
15 30
30 50
15 30
30 50
POWER REQUIREMENTS
VEE, –11.4 to –16.5 V dc
POWER SUPPLY GAIN SENSITIVITY2
VEE = –11.4 to –16.5 V dc
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5)
–12 –18
15 25
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
–12 –18
15 25
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 3)
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 4)
Gain Adjustment Range (Figure 3)
Bipolar Zero Adjustment Range
± 0.25
± 0.15
± 0.1
± 0.05
؎0.25
؎0.15
± 0.25
± 0.15
± 0.1
± 0.05
؎0.25
؎0.1
REFERENCE INPUT
Input Impedance
15 20 25
15
20 25
POWER DISSIPATION
180 300
180 300
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants
Reference Voltage
Accuracy
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to 10 V [p-p], Sine Wave
Frequency for 1/2 LSB [p-p] Feedthrough)
Output Slew Rate 10%–90%
90%–10%
Output Settling Time (All Bits ON and a 0 V–10 V
Step Change in Reference Voltage)
Two (2): Bipolar Operation at Digital Input Only
1 V to 10 V, Unipolar
10 Bits (± 0.05% of Reduced F.S.) for 1 V dc Reference Voltage
40
5
1
1.5 μs to 0.01% F.S.
CONTROL AMPLIFIER
Full Power Bandwidth
Small-Signal Closed-Loop Bandwidth
300
1.8
NOTES
1The digital input levels are guaranteed but not tested over the temperature range.
2The power supply gain sensitivity is tested in reference to a VEE of –1.5 V dc.
Specifications subject to change without notice.
Unit
V
V
μA
μA
Bits
mA
mA
kΩ
% of F.S. Range
% of F.S. Range
pF
V
LSB
% of F.S. Range
LSB
% of F.S. Range
LSB
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ns
ns
ns
mA
ppm of F.S./%
V
V
V
V
V
% of F.S. Range
% of F.S. Range
% of F.S. Range
% of F.S. Range
kΩ
mW
kHz typ
mA/μs
mA/μs
kHz
MHz
–4– REV. F

5 Page

AD565A arduino
AD565A
CONNECTING THE AD566A FOR BUFFERED VOLTAGE
OUTPUT
The standard current-to-voltage conversion connections using an
operational amplifier are shown in Figures 4, 5, and 6 with the
preferred trimming techniques. If a low offset operational amplifier
(OP77, AD741L, OP07) is used, excellent performance can be
obtained in many situations without trimming (an op amp with
less than 0.5 mV max offset voltage should be used to keep offset
errors below 1/2 LSB). If a 50 Ω fixed resistor is substituted for the
100 Ω trimmer, unipolar zero typically is within ±1/2 LSB (plus op
amp offset), and full-scale accuracy is within 0.1% (0.25% max).
Substituting a 50 Ω resistor for the 100 Ω bipolar offset trimmer
gives a bipolar zero error typically within ± 2 LSB (0.05%).
The AD509 is recommended for buffered voltage-output
applications that require a settling time to ± 1/2 LSB of 1 μs. The
feedback capacitor is shown with the optimum value for each
application; this capacitor is required to compensate for the
25 pF DAC output capacitance.
FIGURE 4. UNIPOLAR CONFIGURATION
This configuration provides a unipolar 0 V to 10 V output range.
In this mode, the bipolar terminal, Pin 7, should be grounded if not
used for trimming.
AD566A
100
100k
BIPOLAR OFF
+15V
R1
50k
–15V
20V SPAN
9.95k5k
10V SPAN
R2
100
REF
IN 19.95k
0.5mA
+V 10V EREF
AD561
20k
IREF
REF
GND
POWER
GND
5k
IO 8k
DAC
IOUT =
4 ؋ IREF
؋ CODE
CODE
INPUT
–VEE
MSB
LSB
DAC
OUT
10pF
AD509
2.4k
Figure 4. 0 V to 10 V Unipolar Voltage Output
STEP II . . . GAIN ADJUST
Turn all bits ON and adjust 100 Ω gain trimmer, R2, until the
output is 9.9976 V. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 V.) If a 10.2375 V full scale is desired
(exactly 2.5 mV/bit), insert a 120 Ω resistor in series with the
gain resistor at Pin 10 to the op amp output.
FIGURE 5. BIPOLAR CONFIGURATION
This configuration provides a bipolar output voltage from
–5.000 V to +4.9976 V, with positive full scale occurring with
all bits ON (all 1s).
R1
100
BIPOLAR OFF
AD566A
9.95k5k
20V SPAN
10V SPAN
R2
100
REF
IN 19.95k
0.5mA
+V 10V EREF
AD561
20k
IREF
REF
GND
POWER
GND
5k
IO 8k
DAC
IOUT =
4 ؋ IREF
؋ CODE
CODE
INPUT
–VEE
MSB
LSB
DAC
OUT
10pF
AD509
2.4k
Figure 5. ±5 V Bipolar Voltage Output
STEP I . . . OFFSET ADJUST
Turn OFF all bits. Adjust 100 Ω trimmer R1 to give –5.000
output V.
STEP II . . . GAIN ADJUST
Turn ON all bits. Adjust 100 Ω gain trimmer R2 to give a read-
ing of +4.9976 V.
Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
an op amp trim is unnecessary unless the untrimmed offset drift
of the op amp is excessive.
STEP I . . . ZERO ADJUST
Turn all bits OFF and adjust zero trimmer, R1, until the output
reads 0.000 V (1 LSB = 2.44 mV). In most cases, this trim is
not needed, but Pin 7 should then be connected to Pin 12.
REV. F
–9–

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