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16-/14-Bit DACs - Analog Devices

Número de pieza AD5545
Descripción 16-/14-Bit DACs
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo
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AD5545 datasheet

1 Page

AD5545 pdf
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VDD to GND
VREF to GND
Logic Inputs to GND
V(IOUT) to GND
Input Current to Any Pin except
Supplies
Package Power Dissipation
Thermal Resistance θJA
16-Lead TSSOP
Maximum Junction Temperature
(TJ max)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
RU-16 (Vapor Phase, 60 sec)
RU-16 (Infrared, 15 sec)
Rating
–0.3 V to +8 V
–18 V to +18 V
–0.3 V to +8 V
–0.3 V to VDD + 0.3 V
±50 mA
(TJ max – TA)/θJA
150°C/W
150°C
–40°C to +85°C
–65°C to +150°C
215°C
220°C
AD5545/AD5555
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. I | Page 5 of 23

5 Page

AD5545 arduino
AD5545/AD5555
Data Sheet
SERIAL DATA INTERFACE
The AD5545/AD5555 use a minimum 3-wire (CS, SDI, CLK)
serial data interface for single channel update operation. With
Table 7 as an example (AD5545), users can tie LDAC low and
RS high, and then pull CS low for an 18-bit duration. New serial
data is then clocked into the serial-input register in an 18-bit
data-word format with the MSB bit loaded first. Table 8 defines
the truth table for the AD5555. Data is placed on the SDI pin
and clocked into the register on the positive clock edge of CLK.
For the AD5545, only the last 18-bits clocked into the serial
register are interrogated when the CS pin is strobed high,
transferring the serial register data to the DAC register and
updating the output. If the applied microcontroller outputs
serial data in different lengths than the AD5545, such as 8-bit
bytes, three right justified data bytes can be written to the
AD5545. The AD5545 ignores the six MSB and recognizes the
18 LSB as valid data. After loading the serial register, the rising
edge of CS transfers the serial register data to the DAC register
and updates the output; during the CS strobe, the CLK should
not be toggled.
If users want to program each channel separately but update them
simultaneously, program LDAC and RS high initially, then pull
CS low for an 18-bit duration and program DAC A with the
proper address and data bits. CS is then pulled high to latch data
to the DAC A register. At this time, the output is not updated. To
load DAC B data, pull CS low for an 18-bit duration and program
DAC B with the proper address and data, then pull CS high to
latch data to the DAC B register. Finally, pull LDAC low and then
high to update both the DAC A and DAC B outputs
simultaneously.
Table 6 shows that each DAC A and DAC B can be individually
loaded with a new data value. In addition, a common new data
value can be loaded into both DACs simultaneously by setting Bit
A1 = A0 = high. This command enables the parallel combination
of both DACs, with IOUTA and IOUTB tied together, to act as one
DAC with significant improved noise performance.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to digital ground (DGND) and VDD as shown in
Figure 19.
VDD
DIGITAL
INPUTS
5k
DGND
02918-0-007
Figure 19. Equivalent ESD Protection Circuits
Table 4. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB
LSB
Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 Note that only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the
decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5545 shift register are ignored; only the last 18 bits clocked in
are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 5. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB
LSB
Bit Position
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 Note that only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the
decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5555 shift register are ignored; only the last 16 bits clocked in
are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 6. Address Decode
A1 A0
00
01
10
11
DAC Decoded
None
DAC A
DAC B
DAC A and DAC B
Rev. I | Page 10 of 23

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