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PDF FDS6994S Data sheet ( Hoja de datos )

Número de pieza FDS6994S
Descripción MOSFET ( Transistor )
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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October 2006
FDS6994S
Dual Notebook Power Supply N-Channel PowerTrenchSyncFet
General Description
The FDS6994S is designed to replace two single SO-8
MOSFETs and Schottky diode in synchronous DC:DC
power supplies that provide various peripheral voltages
for notebook computers and other battery powered
electronic devices. FDS6994S contains two unique
30V, N-channel, logic level, PowerTrench MOSFETs
designed to maximize power conversion efficiency.
The high-side switch (Q1) is designed with specific
emphasis on reducing switching losses while the low-
side switch (Q2) is optimized to reduce conduction
losses. Q2 also includes an integrated Schottky diode
using Fairchild’s monolithic SyncFET technology.
Features
Q2: Optimized to minimize conduction losses
Includes SyncFET Schottky body diode
8.2A, 30V
RDS(on) = 15 m@ VGS = 10V
RDS(on) = 17.5 m@ VGS = 4.5V
Q1: Optimized for low switching losses
Low gate charge (85.5 nC typical)
6.9A, 30V
RDS(on) = 21 m@ VGS = 10V
RDS(on) = 26 m@ VGS = 4.5V
D1
D1
D2
D2
SO-8
G1
S1
G2
S2
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
VGSS
ID
PD
TJ, TSTG
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
(Note 1a)
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
RθJC Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
FDS6994S
FDS6994S
13”
2006 Fairchild Semiconductor Corporation
5
6 Q1
7
Q2
8
4
3
2
1
Q2 Q1
30 30
±16 ±16
8.2 6.9
30 20
2
1.6
1
0.9
-55 to +150
Units
V
V
A
W
°C
78 °C/W
40 °C/W
Tape width
12mm
Quantity
2500 units
FDS6994S Rev C2(W)

1 page




FDS6994S pdf
Typical Characteristics for Q2
10
ID =8.2A
8
6
VDS = 10V
15V
20V
4
2
0
0 10 20 30 40 50
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
100
RDS(ON) LIMIT
10
1
VGS = 10V
0.1 SINGLE PULSE
RθJA = 135oC/W
TA = 25oC
1ms
10ms
100ms
1s
10s
DC
100µs
0.01
0.1
1 10
VDS, DRAIN-SOURCE VOLTAGE (V)
100
Figure 9. Maximum Safe Operating Area.
4000
3000
2000
f = 1MHz
VGS = 0 V
Ciss
1000
0
0
Crss
Coss
5 10 15 20 25
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure 8. Capacitance Characteristics.
50
SINGLE PULSE
40 RθJA = 135°C/W
TA = 25°C
30
20
10
0
0.001
0.01
0.1 1 10
t1, TIME (sec)
100 1000
Figure 10. Single Pulse Maximum
Power Dissipation.
1
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
0.001
0.0001
0.001
0.01
0.1
t1, TIME (sec)
1
10
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
RθJA(t) = r(t) * RθJA
RθJA = 135 °C/W
P(pk)
t1
t2
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
100 1000
FDS6994S Rev C2(W)

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