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Número de pieza | FDMC8200S | |
Descripción | MOSFET ( Transistor ) | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
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No Preview Available ! March 2011
FDMC8200S
Dual N-Channel PowerTrench® MOSFET
30 V, 10 mΩ, 20 mΩ
Features
Q1: N-Channel
Max rDS(on) = 20 mΩ at VGS = 10 V, ID = 6 A
Max rDS(on) = 32 mΩ at VGS = 4.5 V, ID = 5 A
Q2: N-Channel
Max rDS(on) = 10 mΩ at VGS = 10 V, ID = 8.5 A
Max rDS(on) = 13.5 mΩ at VGS = 4.5 V, ID = 7.2 A
RoHS Compliant
General Description
This device includes two specialized N-Channel MOSFETs in a
due power33(3mm X 3mm MLP) package. The switch node has
been internally connected to enable easy placement and routing
of synchronous buck converters. The control MOSFET (Q1) and
synchronous MOSFET (Q2) have been designed to provide
optimal power efficiency.
Applications
Mobile Computing
Mobile Internet Devices
General Purpose Point of Load
Pin 1
Bottom
D1
D1
D1
G1
D1
D2/S1
S2
S2
S2
G2
Bottom
VIN VIN
GHSVIN
VIN
SWITCH
NODE
GND
GND
GND
GLS
5 Q2
6
7
8
4
3
2
1
Q1
Power33
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
TC = 25 °C
TC = 25 °C
TA = 25 °C
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
TA = 25°C
Power Dissipation for Single Operation
TA = 25°C
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 4)
(Note 3)
Q1 Q2
30 30
±20 ±20
18 13
23 46
6 1a 8.5 1b
40 27
12
1.9 1a
0.7 1c
32
2.5 1b
1.0 1d
-55 to +150
Units
V
V
A
W
°C
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
65 1a
180 1c
7.5
50 1b
125 1d
4.2
°C/W
Device Marking
FDMC8200S
Device
FDMC8200S
Package
Power 33
Reel Size
13”
Tape Width
12 mm
Quantity
3000 units
©2011 Fairchild Semiconductor Corporation
FDMC8200S Rev.C4
1
www.fairchildsemi.com
1 page Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
10
ID = 6 A
8
VDD = 15 V
6
VDD = 10 V
4
VDD = 20 V
2
0
0246
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
8
1000
100
Ciss
Coss
Crss
f = 1 MHz
VGS = 0 V
10
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. CapacitancevsDrain
to Source Voltage
8
7
6
5
4
TJ = 25 oC
3
TJ = 100 oC
2
TJ = 125 oC
1
0.01
0.1 1
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
7
25
20
15
Limited by Package
10
5
RθJC = 7.5 oC/W
VGS = 10 V
VGS = 4.5 V
0
25 50 75 100 125
Tc, CASE TEMPERATURE (oC)
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
150
15000
1100
10100u0sus
1 ms
1
1
1 m10sms
THTIHSISARAERAEAISIS
0.1 LIMLIIMTEITDEDBYBYrDrSD(Son(o)n)
101m00s ms
1010 sms
0.1
0.01
0.01
SINGLE PULSSIENGLE PULSE
TJ = MAX RATTJE=DMAX RATED
RθJA = 180 oCR/θWJA = 125 oC/W
TC = 25 oC TA = 25 oC
1 s10 s
10DsC
DC
0.0001.01
0.1
1
10 100200
0.01
0.1 1
10
VDS, DRAIN to SOURCE VOLTAGE (V)
VDS, DRAIN to SOURCE VOLTAGE (V)
100200
Figure 11. Forward Bias Safe
Operating Area
100
VGS = 10 V
10
1
0.1
0.001
SINGLE PULSE
RθJA = 125 oC/W
TA = 25 oC
0.01 0.1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 12. Single Pulse Maximum
Power Dissipation
©2011 Fairchild Semiconductor Corporation
FDMC8200S Rev.C4
5
www.fairchildsemi.com
5 Page Dimensional Outline and Pad Layout
©2011 Fairchild Semiconductor Corporation
FDMC8200S Rev.C4
11
www.fairchildsemi.com
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet FDMC8200S.PDF ] |
Número de pieza | Descripción | Fabricantes |
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