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PDF FDML7610S Data sheet ( Hoja de datos )

Número de pieza FDML7610S
Descripción MOSFET ( Transistor )
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FDML7610S Hoja de datos, Descripción, Manual

FDML7610S
PowerTrench® Power Stage
Asymmetric Dual N-Channel MOSFET
Features
Q1: N-Channel
„ Max rDS(on) = 7.5 mΩ at VGS = 10 V, ID = 12 A
„ Max rDS(on) = 12 mΩ at VGS = 4.5 V, ID = 10 A
Q2: N-Channel
„ Max rDS(on) = 4.2 mΩ at VGS = 10 V, ID = 17 A
„ Max rDS(on) = 5.5 mΩ at VGS = 4.5 V, ID = 14 A
„ RoHS Compliant
April 2013
General Description
This device includes two specialized N-Channel MOSFETs in a
dual MLP package.The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Applications
„ Computing
„ Communications
„ General Purpose Point of Load
„ Notebook VCORE
Pin 1
D1 D1 D1
G1
D1
PHASE
(S1/D2)
S2 5
S2 6
Q2
PHASE
4 D1
3 D1
G2S2 S2S2
S2 7
G2 8
2 D1
Q1 1 G1
Top
MLP 3X4.5
Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
PD
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
Power Dissipation for Single Operation
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
TA = 25 °C
TA = 25 °C
Q1 Q2
30 30
±20 ±20
30 28
40
121a
60
171b
40
2.11a
0.81c
40
2.21b
0.91d
-55 to +150
Units
V
V
A
W
°C
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
601a
1501c
4
561b
1401d
3.5
°C/W
Device Marking
FDML7610S
Device
FDML7610S
Package
MLP3X4.5
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
1
www.fairchildsemi.com

1 page




FDML7610S pdf
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
10
ID = 12 A
8
6
4
2
VDD = 10 V
VDD = 15 V
VDD = 20 V
0
0 5 10 15 20
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
2000
1000
Ciss
Coss
100
f = 1 MHz
Crss
VGS = 0 V
10
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. Capacitance vsDrain
to Source Voltage
60
VGS = 10 V
40
VGS = 4.5 V
20 Limited by Package
RθJC = 4 oC/W
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
Figure 9. Maximum Continuous Drain Current vs
Case Temperature
1000
100
100
100us
10
1 ms
1
THIS AREA IS
LIMITED BY rDS(on)
10 ms
100 ms
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 150 oC/W
TA = 25 oC
0.01
0.01 0.1
1
1s
10s
DC
10 100 200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 10. Forward Bias Safe Operating Area
SINGLE PULSE
RθJA = 150 oC/W
TA = 25 oC
10
1
0.5
10-4
10-3
10-2
10-1
1
t, PULSE WIDTH (s)
10
Figure 11. Single Pulse Maximum Power Dissipation
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
5
100 1000
www.fairchildsemi.com

5 Page





FDML7610S arduino
Application Information
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Power Stage Device
Competitors solution
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
11
www.fairchildsemi.com

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