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PDF FDMS3624S Data sheet ( Hoja de datos )
| Número de pieza | FDMS3624S | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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December 2011
FDMS3624S
PowerTrench® Power Stage
25V Asymmetric Dual N-Channel MOSFET
Features
Q1: N-Channel
Max rDS(on) = 5.0 mΩ at VGS = 10 V, ID = 17.5 A
Max rDS(on) = 5.7 mΩ at VGS = 4.5 V, ID = 16 A
Q2: N-Channel
Max rDS(on) = 1.8 mΩ at VGS = 10 V, ID = 30 A
Max rDS(on) = 2.2 mΩ at VGS = 4.5 V, ID = 27 A
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
RoHS Compliant
General Description
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Applications
Computing
Communications
General Purpose Point of Load
Notebook VCORE
Pin 1
Pin 1
G1 D1 D1 D1
D1
PHASE
(S1/D2)
G2S2
S2 S2
Top
Power 56
Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 4)
TC = 25 °C
TA = 25 °C
(Note 3)
TA = 25 °C
TA = 25 °C
Q1 Q2
25 25
±12 ±12
30
17.51a
60
301b
70 120
29
2.21a
1.01c
86
2.51b
1.01d
-55 to +150
Units
V
V
A
mJ
W
°C
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
571a
1251c
3.0
501b
1201d
2.2
°C/W
Device Marking
08OD
07OD
Device
FDMS3624S
Package
Power 56
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
©2011 Fairchild Semiconductor Corporation
FDMS3624S Rev.C2
1
www.fairchildsemi.com
1 page  
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
10
ID = 17.5 A
8
6
4
VDD = 10 V
VDD = 15 V
VDD = 13 V
2
0
0 4 8 12 16 20 24 28
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
2000
1000
100
Ciss
Coss
f = 1 MHz
Crss
VGS = 0 V
10
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. CapacitancevsDrain
to Source Voltage
50
TJ = 25 oC
10
TJ = 100 oC
TJ = 125 oC
1
0.001
0.01 0.1
1
tAV, TIME IN AVALANCHE (ms)
10
Figure9. UnclampedInductive
Switching Capability
50
80
70
60
VGS = 10 V
50
VGS = 4.5 V
40
30
20
Limited by Package
10 RθJC = 3.0 oC/W
0
25 50 75 100 125
TC, CASE TEMPERATURE (oC)
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
150
100
100 μs
10
1 THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 125 oC/W
TA = 25 oC
0.01
0.01
0.1
1
1 ms
10 ms
100 ms
1s
10s
DC
10 100200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
1000
100
SINGLE PULSE
RθJA = 125 oC/W
10
1
0.5
10-4 10-3 10-2 10-1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 12. Single Pulse Maximum
Power Dissipation
©2011 Fairchild Semiconductor Corporation
FDMS3624S Rev.C2
5
www.fairchildsemi.com
5 Page 
0.10 C
(2X)
8
5.10
4.90
PKG
CL
5
PKG CL
PIN # 1
INDICATOR
14
TOP VIEW
A
B
6.25
5.90
0.10 C
(2X)
0.63
2.15
4.16
2.13
0.63
4.00
CL
8 76
12 3
0.59
3.18
5.10
1.27 TYP
0.65 TYP
5
2.52
1.60
KEEP OUT AREA
0.00 CL
1.21
2.31
4 3.15
SEE
DETAIL A
RECOMMENDED LAND PATTERN
FOR SAWN / PUNCHED TYPE
SIDE VIEW
0.45
0.25
(6X)
0.65
0.38
1
3.16
2.80
23
0.10
0.05
0.70
0.36
CAB
C
4 1.34
1.12
4.08
3.70
0.66±.05
2.25
2.05
0.65 8
0.38
0.44
0.24
76
1.27
3.81
1.02
5 0.82
0.61
0.31
(8X)
BOTTOM VIEW
0.10 C
8X
0.08 C
1.10
0.90
0.35
0.15
0.05
0.00
C
SEATING
PLANE
(SCALE: 2X)
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FDMS3624S.PDF ] | |
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