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Número de pieza | FDMS3602S | |
Descripción | MOSFET ( Transistor ) | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
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No Preview Available ! FDMS3602S
PowerTrench® Power Stage
July 2016
25 V Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
Max rDS(on) = 5.6 mΩ at VGS = 10 V, ID = 15 A
Max rDS(on) = 8.1 mΩ at VGS = 4.5 V, ID = 14 A
Q2: N-Channel
Max rDS(on) = 2.2 mΩ at VGS = 10 V, ID = 26 A
Max rDS(on) = 3.4 mΩ at VGS = 4.5 V, ID = 22 A
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
RoHS Compliant
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Applications
Computing
Communications
General Purpose Point of Load
Notebook VCORE
Pin 1
Server
G1 D1 D1 D1
D1
S2 5
Q2
4 D1
PHASE
(S1/D2)
G2S2
S2 S2
Top
Power 56
Bottom
MOSFET Maximum Ratings TA = 25°C unless otherwise noted.
S2 6
S2 7
G2 8
PHASE
3 D1
2 D1
Q1 1 G1
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
TA = 25°C
TA = 25°C
Q1 Q2
25 25
±20 ±20
30 40
65
151a
135
261b
40
504
2.21a
1.01c
100
1445
2.51b
1.01d
-55 to +150
Units
V
V
A
mJ
W
°C
Thermal Characteristics
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
571a
1251c
3.5
501b
1201d
2
°C/W
Device Marking
22OA
N7OC
Device
FDMS3602S
©2011 Fairchild Semiconductor Corporation
FDMS3602S Rev.1.12
Package
Power 56
1
Reel Size
13”
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com
1 page Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.
10
ID = 15 A
8
6
4
VDD = 10 V
VDD = 13 V
VDD = 16 V
2
0
0 5 10 15 20
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
2000
1000
Ciss
Coss
100
Crss
f = 1 MHz
VGS = 0 V
10
0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure8. Capacitancevs.Drain
to Source Voltage
25
20
10
TJ = 25 oC
TJ = 100 oC
TJ = 125 oC
1
0.01
0.1 1 10
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
100
80
RθJC = 3.5 oC/W
60
VGS = 10 V
40
VGS = 4.5 V
20
Limited by Package
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
Figure 10. Maximum Continuous Drain
Current vs. Case Temperature
100
100 μs
10
1 ms
1
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 125 oC/W
TA = 25 oC
0.01
0.01 0.1
1
10 ms
100 ms
1s
10s
DC
10 100 200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
1000
100
SINGLE PULSE
RθJA = 125 oC/W
TA = 25 oC
10
1
0.5
10-4 10-3 10-2 10-1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 12. Single Pulse Maximum
Power Dissipation
©2011 Fairchild Semiconductor Corporation
FDMS3602S Rev.1.12
5
www.fairchildsemi.com
5 Page Application Information
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Power Stage Device
Competitors solution
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
©2011 Fairchild Semiconductor Corporation
FDMS3602S Rev.1.12
11
www.fairchildsemi.com
11 Page |
Páginas | Total 17 Páginas | |
PDF Descargar | [ Datasheet FDMS3602S.PDF ] |
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