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PDF FDBL0210N80 Data sheet ( Hoja de datos )
| Número de pieza | FDBL0210N80 | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | Fairchild Semiconductor | |
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FDBL0210N80
N-Channel PowerTrench® MOSFET
80 V, 240 A, 2.0 mΩ
April 2015
Features
Typical RDS(on) = 1.5 mΩ at VGS = 10V, ID = 80 A
Typical Qg(tot) = 130 nC at VGS = 10V, ID = 80 A
UIS Capability
RoHS Compliant
Applications
Industrial Motor Drive
Industrial Power Supply
Industrial Automations
Battery Operated tools
Battery Protection
Solar Inverters
UPS and Energy Inverters
Energy Storage
Load Switch
D
G
S
For current package drawing, please refer to the Fairchild web‐
site at http://www.fairchildsemi.com/dwg/PS/PSOF08A.pdf.
MOSFET Maximum Ratings TJ = 25°C unless otherwise noted.
Symbol
Parameter
VDSS
VGS
ID
Drain-to-Source Voltage
Gate-to-Source Voltage
Drain Current - Continuous (VGS=10) (Note 1)
Pulsed Drain Current
EAS Single Pulse Avalanche Energy
PD
Power Dissipation
Derate Above 25oC
TJ, TSTG
RθJC
RθJA
Operating and Storage Temperature
Thermal Resistance, Junction to Case
Maximum Thermal Resistance, Junction to Ambient
TC = 25°C
TC = 25°C
(Note 2)
(Note 3)
Ratings
80
±20
240
See Figure 4
512
357
2.38
-55 to + 175
0.42
43
Units
V
V
A
mJ
W
W/oC
oC
oC/W
oC/W
Notes:
1: Current is limited by silicon.
2: Starting TJ = 25°C, L = 0.25mH, IAS = 64A, VDD = 80V during inductor charging and VDD = 0V during time in avalanche.
3: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder
mounting surface
presented here is
of the
based
drain pins. RθJC is
on mounting on a 1
guaranteed by design,
in2 pad of 2oz copper.
while
RθJAis
determined
by
the
board
design.
The maximum rating
Package Marking and Ordering Information
Device Marking
FDBL0210N80
Device
FDBL0210N80
Package
MO-299A
Reel Size
-
Tape Width
-
Quantity
-
©2015 Fairchild Semiconductor Corporation
FDBL0210N80 Rev. 1.0
1
www.fairchildsemi.com
1 page  
Typical Characteristics
50
ID = 80A
40
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
30
20 TJ = 175oC
TJ = 25oC
10
0
246 8
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 11. RDSON vs. Gate Voltage
10
2.4
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
2.0
1.6
1.2
0.8
0.4
-80
ID = 80A
VGS = 10V
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE(oC)
200
Figure 12. Normalized RDSON vs. Junction
Temperature
1.5
VGS = VDS
ID = 250μA
1.2
0.9
0.6
0.3
0.0
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE(oC)
200
Figure 13. Normalized Gate Threshold Voltage vs.
Temperature
1.10
ID = 5mA
1.05
1.00
0.95
0.90
-80
-40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
Figure 14. Normalized Drain to Source
Breakdown Voltage vs. Junction Temperature
100000
10000
1000
Ciss
Coss
100 Crss
f = 1MHz
VGS = 0V
10
0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
Figure 15. Capacitance vs. Drain to Source
Voltage
10
ID = 80A
8
6
VDD = 32V
40V
48V
4
2
0
0 30 60 90 120 150
Qg, GATE CHARGE(nC)
Figure 16. Gate Charge vs. Gate to Source
Voltage
©2015 Fairchild Semiconductor Corporation
FDBL0210N80 Rev. 1.0
5
www.fairchildsemi.com
5 Page | ||
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| PDF Descargar | [ Datasheet FDBL0210N80.PDF ] | |
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