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PDF FDPC8011S Data sheet ( Hoja de datos )

Número de pieza FDPC8011S
Descripción MOSFET ( Transistor )
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FDPC8011S Hoja de datos, Descripción, Manual

FDPC8011S
PowerTrench® Power Clip
25V Asymmetric Dual N-Channel MOSFET
October 2014
Features
General Description
Q1: N-Channel
„ Max rDS(on) = 7.3 mΩ at VGS = 4.5 V, ID = 12 A
Q2: N-Channel
„ Max rDS(on) = 2.1 mΩ at VGS = 4.5 V, ID = 24 A
„ Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
„ MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
„ RoHS Compliant
This device includes two specialized N-Channel MOSFETs in a
dual package. The switch node has been internally connected to
enable easy placement and routing of synchronous buck
converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Applications
„ Computing
„ Communications
„ General Purpose Point of Load
Pin 1
Top
V+
LS
Pin 1
GND
GND
V+
(HSD
HSG
GND
(LSS
HSG SW
SW
SW
SW
SW
3.3 mm x 3.3 mm
Bottom
SW
PAD9
V+(HSD)
PAD10
GND(LSS)
V+ HSG
LSG SW
GND SW
GND SW
SW
V+
LSG
GND
GND
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
Thermal Characteristics
TC = 25 °C
TA = 25 °C
(Note 3)
TA = 25 °C
TA = 25 °C
Q1 Q2
25 25
12 12
20
131a
60
271b
40 120
21
1.61a
0.81c
97
2.01b
0.91d
-55 to +150
Units
V
V
A
mJ
W
°C
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
771a
1511c
5.0
631b
1351d
3.5
°C/W
Device Marking
13OD/15OD
Device
FDPC8011S
Package
Power Clip 33
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
1
www.fairchildsemi.com

1 page




FDPC8011S pdf
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
10
ID = 13 A
8
2000
1000
Ciss
6
VDD = 10 V
VDD = 15 V
4
VDD = 13 V
2
0
0 4 8 12 16 20
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
50
TJ = 25 oC
10
TJ = 125 oC
TJ = 100 oC
1
0.001
0.01 0.1
1
tAV, TIME IN AVALANCHE (ms)
10
Figure 9. Unclamped Inductive
Switching Capability
50
Coss
100
f = 1 MHz
Crss
VGS = 0 V
10
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure8. Capacitance vsDrain
to Source Voltage
30
60
50 VGS = 10 V
40
30
VGS = 4.5 V
20
10 Limited by Package
RθJC = 5.0 oC/W
0
25 50 75 100 125
TC, CASE TEMPERATURE (oC)
150
Figure 10. Maximum Continuous Drain
Current vs. Ambient Temperature
100 1000
SINGLE PULSE
RθJA = 151 oC/W
10 100 μs
100
1
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 151 oC/W
TA = 25 oC
0.01
0.01
0.1
1
10
VDS, DRAIN to SOURCE VOLTAGE (V)
1 ms
10 ms
100 ms
1s
10s
DC
100
Figure 11. Forward Bias Safe
Operating Area
10
1
0.5
10-4 10-3 10-2 10-1 100 101 100 1000
t, PULSE WIDTH (sec)
Figure 12. Single Pulse Maximum
Power Dissipation
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
5
www.fairchildsemi.com

5 Page





FDPC8011S arduino
Application Information
Typical Application Diagram (Synchronous Rectifier Buck Converter)
Figure 1.Power Clip in Buck Converter Topology
As shown in Figure 1, in the Power Clip package Q1 is the High Side MOSFET (Control MOSFET) and Q2 is the Low Side MOSFET
(Synchronous MOSFET). Figure 2 below shows the package pin out. The blue overlay on the drawing indicates a typical PCB land
pattern for the part.
Figure 2.Top View of Power Clip
Table 1 Pin Information shows the name and description of each pin.
Number
PIN
Name
Description
1 HSG
Gate signal input of Q1 Gate
2,3,4
SW
Switch or Phase node, Source of Q1 and Drain of Q2
5,6,PAD 10 GND,GND(LSS) PAD Ground, Source of Q2
7 LSG
Gate signal input of Q2 Gate
8,PAD 9
V+, V+(HSD) PAD
Table 1. Pin Information
Input voltage of SR Buck converter, Drain of Q1
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
11
www.fairchildsemi.com

11 Page







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