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Número de pieza | FDMD86100 | |
Descripción | MOSFET ( Transistor ) | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
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FDMD86100
Dual N-Channel Shielded Gate PowerTrench® MOSFET
100 V, 39 A, 10.5 mΩ
Features
General Description
Common source configuration to eliminate PCB routing
Large source pad on bottom of package for enhanced
thermals
Shielded Gate MOSFET Technology
Max rDS(on) = 10.5 mΩ at VGS = 10 V, ID = 10 A
Max rDS(on) = 17.3 mΩ at VGS = 6 V, ID = 7.8 A
Ideal for flexible layout in secondary side synchronous
rectification
Termination is Lead-free and RoHS Compliant
100% UIL tested
This package integrates two N-Channel devices connected
internally in common-source configuration and incorporates
Shielded Gate technology. This enables very low package
parasitics and optimized thermal path to the common source pad
on the bottom. Provides a very small footprint (5 x 6 mm) for
higher power density.
Applications
Isolated DC-DC Synchronous Rectifiers
Common Ground Load Switches
Top Bottom
Pin 1
Pin 1
G1
D1
D1
D1
S1 / S2
D2
D2
D2
G2
G1 1
D1 2
D1 3
D1 4
S1,S2 to backside
8 D2
7 D2
6 D2
5 G2
Power 5 x 6
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Drain Current
-Continuous
-Continuous
-Continuous
-Pulsed
TC = 25 °C
TC = 100 °C
TA = 25 °C
Single Pulse Avalanche Energy
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 5)
(Note 5)
(Note 1a)
(Note 4)
(Note 3)
(Note 1a)
Ratings
100
±20
39
24
10
299
337
33
2.2
-55 to +150
Units
V
V
A
mJ
W
°C
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Note 1a)
3.7
55
°C/W
Device Marking
FDMD86100
Device
FDMD86100
Package
Power 5 x 6
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
©2015 Fairchild Semiconductor Corporation
FDMD86100 Rev.C1
1
www.fairchildsemi.com
1 page Typical Characteristics TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.001
10-5
PDM
SINGLE PULSE
t1
t2
NOTES:
ZθJC(t) = r(t) x RθJC
RθJC = 3.7 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Case Transient Thermal Response Curve
1
©2015 Fairchild Semiconductor Corporation
FDMD86100 Rev.C1
5
www.fairchildsemi.com
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet FDMD86100.PDF ] |
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