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PDF CD4029BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4029BMS | |
| Descripción | CMOS Presettable Up/Down Counter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4029BMS
December 1992
CMOS Presettable Up/Down Counter
Features
• High-Voltage Type (20V Rating)
• Medium Speed Operation: 8MHz (Typ.) at CL = 50pF
and VDD - VSS = 10V
• Multi-Package Parallel Clocking for Synchronous High
Speed Output Response or Ripple Clocking for Slow
Clock Input Rise and Fall Times
• “Preset Enable” and Individual “Jam” Inputs Provided
• Binary or Decade Up/Down Counting
• BCD Outputs in Decade Mode
• 100% Tested for Maximum Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Device’s
Applications
• Programmable Binary and Decade Counting/Fre-
quency Synthesizers-BCD Output
• Analog to Digital and Digital to Analog Conversion
• Up/Down Binary Counting
• Difference Counting
• Magnitude and Sign Generation
• Up/Down Decade Counting
Description
CD4029BMS consists of a four-stage binary or BCD-decade up/
down counter with provisions for look-ahead carry in both count-
ing modes. The inputs consist of a single CLOCK, CARRY-IN
(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET
ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a
CARRY OUT signal are provided as outputs.
A high PRESET ENABLE signal allows information on the JAM
INPUTS to preset the counter to any state asynchronously with
the clock. A low on each JAM line, when the PRESET-ENABLE
signal is high, resets the counter to its zero count. The counter is
advanced one count at the positive transition of the clock when
the CARRY-IN and PRE-SET ENABLE signals are low.
Advancement is inhibited when the CARRY-IN or PRESET
ENABLE signals are high. The CARRY-OUT signal is normally
high and goes low when the counter reaches its maximum count
in the UP mode or the minimum count in the DOWN mode pro-
vided the CARRY-IN signal is low. The CARRY-IN signal in the
low state can thus be considered a CLOCK ENABLE. The
CARRY-IN terminal must be connected to VSS when not in use.
Binary counting is accomplished when the BINARY/DECADE
input is high; the counter counts in the decade mode when the
BINARY/DECADE input is low. The counter counts up when the
UP/DOWN input is high, and down when the UP/DOWN input is
low. Multiple packages can be connected in either a parallel-
clocking or a ripple-clocking arrangement as shown in Figure 17.
Parallel clocking provides synchronous control and hence faster
response from all counting outputs. Ripple-clocking allows for
longer clock input rise and fall times.
The CD4029BMS is supplied in these 16-lead outline packages:
Braze Seal DIP H4X
Frit Seal DIP
H1F
Ceramic Flatpack H6W
Pinout
CD4029BMS
TOP VIEW
PRESET ENABLE 1
Q4 2
JAM 4 3
JAM 1 4
CARRY IN 5
Q1 6
CARRY OUT 7
VSS 8
16 VDD
15 CLOCK
14 Q3
13 JAM 3
12 JAM 2
11 Q2
10 UP/DOWN
9 BINARY/DECADE
Functional Diagram
PRESET
ENABLE
CARRY IN
(CLOCK
1
ENABLE) 5
JAM INPUTS
1 2 3 4 VDD
4 12 13 3
16
6 Q1
BINARY/
DECADE 9
UP/DOWN 10
CLOCK 15
11 Q2
Q3
14
BUFFERED
OUTPUTS
Q4
2
7
8
VSS
CARRY
OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-798
File Number 3304
1 page  
Specifications CD4029BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Minimum Preset Enable
Pulse Width
Input Capacitance
SYMBOL
CONDITIONS
TW VDD = 5V
VDD = 10V
VDD = 15V
CIN Any Input
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
+25oC
+25oC
+25oC
+25oC
MIN
-
-
-
-
MAX
130
70
50
7.5
UNITS
ns
ns
ns
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. From Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge.
5. If more than one unit is cascaded in the parallel clocked application, tr CL should be made ≤ the sum of the fixed propagation delay at
15pF and the transition time of the carry output driving stage for the estimated capacitive load. This measurement was made with a de-
coupling capacitor (>1µF) between VDD and VSS.
6. From Carry In to Clock Edge.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
IDD VDD = 20V, VIN = VDD or GND
VNTH VDD = 10V, ISS = -10µA
∆VTN VDD = 10V, ISS = -10µA
VTP
∆VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES
1, 4
1, 4
1, 4
1, 4
1, 4
1
1, 2, 3, 4
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-2.8
-
MAX
25
-0.2
±1
+25oC
+25oC
0.2 2.8
- ±1
+25oC
+25oC
VOH > VOL <
VDD/2 VDD/2
- 1.35 x
+25oC
Limit
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns
3. See Table 2 for +25oC limit.
4. Read and Record
UNITS
µA
V
V
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 1.0µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
7-802
5 Page 
Timing Diagrams (Continued)
UP/DOWN
PRESET
ENABLE
CD4029BMS
“RIPPLE CLOCKING”
UP/D PE J1 J2 J3 J4
CI
CD4029
CO
B/D CL Q1 Q2 Q3 Q4
UP/D PE J1 J2 J3 J4
CI
CD4029
CO
B/D CL Q1 Q2 Q3 Q4
UP/D PE J1 J2 J3 J4
CI
CD4029
CO
B/D CL Q1 Q2 Q3 Q4
CLOCK
BINARY/
DECADE
1/4 CD4071B
1/4 CD4071B
RIPPLE CLOCKING MODE:
THE UP/DOWN CONTROL CAN BE CHANGED AT ANY COUNT. THE ONLY
RESTRICTION ON CHANGING THE UP/DOWN CONTROL IS THAT THE CLOCK
INPUT TO THE FIRST COUNTING STAGE MUST BE HIGH. FOR CASCADING
COUNTERS OPERATING IN A FIXED UP-COUNT OR DOWN-COUNT MODE,
THE OR GATES ARE NOT REQUIRED BETWEEN STAGES, AND CO IS CON-
NECTED DIRECTLY TO THE CL INPUT OF THE NEXT STAGE WITH CI
GROUNDED.
FIGURE 13. CASCADING COUNTER PACKAGES (Continued)
Chip Dimensions and Pad Layout
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-808
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CD4029BMS.PDF ] | |
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