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PDF EDI88257CA Data sheet ( Hoja de datos )
| Número de pieza | EDI88257CA | |
| Descripción | 256K x 8 Monolithic SRAM | |
| Fabricantes | White Electronic Designs | |
| Logotipo |  |
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White Electronic Designs
EDI88257CA
256Kx8 Monolithic SRAM
FEATURES
Access Times of 20, 25, 35, 45, 55ns
Data Retention Function (LPA Versions)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Organized as 256Kx8
Commercial, Industrial and Military Temperature
Ranges
JEDEC Approved Evolutionary Pinout
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)
Single +5V (±10%) Supply Operation
The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic
CMOS Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary
standard for the two megabit device. The device is
upgradeable to the 512Kx8 SRAM, the EDI88512CA. Pin
1 becomes the higher order address.
A Low Power version, EDI88257LPA, offers a data retention
function for battery back-up opperation. Military product is
available compliant to Appendix A of MIL-PRF-38535.
This product is subject to change without notice.
FIGURE 1 – PIN CONFIGURATION
32 DIP
TOP VIEW
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
VSS 16
32 VCC
31 A15
30 A17
29 WE#
28 A13
27 A8
26 A9
25 A11#
24 OE
23 A10
22 CS#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
BLOCK DIAGRAM
Memory Array
PIN DESCRIPTION
I/O0-7
A0-17
WE#
CS#
OE#
VCC
VSS
NC
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
A0-17
Address
Buffer
Address
Decoder
I/O
Circuits
I/O0-7
WE#
CS
OE#
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2000
Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
EDI88257CA
DATA RETENTION CHARACTERISTICS (EDI88512LP ONLY)
-55°C ≤ TA ≤ +125°C
Characteristic
Low Power Version only
Sym Conditions Min Typ Max
Data Retention Voltage
VCC VCC = 2.0V
2
–
–
Data Retention Quiescent Current
ICCDR
CS# ≥ VCC -0.2V
–
–
2
Chip Disable to Data Retention Time
Operation Recovery Time
tCDR VIN ≥ VCC -0.2V
0
TR
or VIN ≤ 0.2V
tAVAV
–
–
–
–
Units
V
µA
ns
ns
FIGURE 5 – DATA RETENTION - CS# CONTROLLED
DATA RETENTION MODE
VCC
4.5V 4.5V
VCC
tCDR
tR
CS# CS# = VCC -0.2V
DATA RETENTION, CS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2000
Rev. 2
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet EDI88257CA.PDF ] | |
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