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PDF IR35201 Data sheet ( Hoja de datos )
| Número de pieza | IR35201 | |
| Descripción | 8+0/7+1/6+2 Dual Output Digital Multi-Phase Controller | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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8+0/7+1/6+2 Dual Output Digital Multi-Phase Controller
IR35201
FEATURES
Ultra Low Quiescent Power Dual output 8 phase
(8+0/7+1/ 6+2) PWM Controller
VR12 Rev 1.7, VR12.5 Rev 1.5, IMVP8 Rev 1.2, AMD
SVI2, and Memory VR modes
Switching frequency from 194KHz to 2MHz per phase
in 56 steps
IR Efficiency Shaping Features including Dynamic
Phase Control and Automatic Power State Switching
Programmable 1-phase or 2-phase operation for Light
Loads and Active Diode Emulation for very Light
Loads
IR Adaptive Transient Algorithm (ATA) on both loops
minimizes output bulk capacitors and system cost
Auto-Phase Detection with PID Coefficient auto-
scaling
Fault Protection: OVP, UVP, OCP, OTP, CAT_FLT
I2C/SMBus/PMBus system interface for reporting of
Temperature, Voltage, Current & Power telemetry for
both loops
Multiple Time Programming (MTP) with integrated
charge pump for easy non-volatile programming
Compatible with 3.3V tri-state drivers
+3.3V supply voltage; -40oC to 85oC ambient
operation; -40oC to 125oC junction
Pb-Free, RoHS, 7x7mm 56-pin, 0.4mm pitch QFN
APPLICATIONS
VR12, VR12.5 and IMVP8 (overclocking only), AMD
SVI2 based systems
Servers and High End Desktop CPU VRs
High Performance Graphics Processors, Memory VR
DESCRIPTION
The IR35201 is a dual-loop digital multi-phase
buck controller designed for CPU voltage
regulation, and is fully compliant with Intel®, VR12
Rev 1.7, VR12.5 Rev 1.5, IMVP82 Rev 1.2, and
AMD SVI2 REV 1.06 specifications.
The IR35201 includes IR’s Efficiency Shaping
Technology to deliver exceptional efficiency at
minimum cost across the entire load range. IR’s
Dynamic Phase Control adds/drops phases based
upon load current. The IR35201 can be configured
to enter 1 or 2-phase PS1 operation and active
diode emulation mode automatically or by
command.
IR’s unique Adaptive Transient Algorithm (ATA),
based on proprietary non-linear digital PWM
algorithms, minimizes output bulk capacitors.
IR35201 has 127 possible address values for both
the PMBus and I2C bus interfaces. The device
configuration can be easily defined using the IR
PowIRCenter GUI, and is stored in the on-chip
Non-Volatile Memory (NVM). This reduces external
components and minimizes the package size.
The IR35201 provides extensive OVP, UVP, OCP,
OTP & CAT_FLT fault protection, and includes
thermistor based temperature sensing or per
phase temperature reporting when using the IR
powIRstage. The controller is designed to work
with either Rdson current sense PowIRstages or
with DCR current sense.
The IR35201 also includes numerous VR design
simplifying and differentiating features, like register
diagnostics, which enable fast time-to-market.
ORDERING INFORMATION
Base Part
Number
IR35201
Package Type
56-pin, QFN 7 mm x 7 mm
Standard Pack
Form
Quantity
Tape and Reel
3000
Orderable
Part Number
IR35201MxxyyTRP1
IR35201
56-pin, QFN 7 mm x 7 mm
Tape and Reel
3000
IR35201MTRPBF
IR35201
56-pin, QFN 7 mm x 7 mm
Tray
4900
IR35201MTYPBF
Notes:
1.
2.
Customer Specific Configuration File, where xx = Customer ID and yy = Configuration File (Codes assigned by IR Marketing).
IR35201 is not intended for application where ultra low power PS4 shutdown functionality is required.
1 www.irf.com | © 2016 International Rectifier
February 8, 2015 | V1.6
1 page  
8+0/7+1/6+2 Dual Output Digital Multi-Phase Controller
IR35201
PIN DESCRIPTIONS
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIN NAME TYPE
PIN DESCRIPTION
ISEN6
RCSP
RCSM
VRDY2
VSEN
VRTN
NC
I_IN
TSEN1
CFILT
VRDY1
EN_L2
PWROK
CAT_FLT
NC
VINSEN
NC
SV_ADDR
VDDIO
SV_ALERT#
SVT
SV_CLK
SV_DIO
VRHOT_ICRIT#
A [I]
A [O]
A [O]
D [O]
A [I]
A [I]
A [I]
A [I]
A [O]
D [O]
D[I]
D[I]
D[O]
A [I]
A[I]
A[P]
D [O]
D [I]
D [B]
D [O]
Phase 6 Current Sense Input. Phase 6 sensed current input (+).Short to GND if not used.
Resistor Current Sense Positive. This pin is connected to an external network to set the load
line slope, bandwidth and temperature compensation for Loop 1.
Resistor Current Sense Minus. This pin is connected to an external network to set the load line
slope, bandwidth and temperature compensation for Loop 1.
Voltage Regulator Ready Output (Loop #2). Open-drain output that asserts high when the VR
has completed soft-start to Loop #2 boot voltage. Pull-up to an external voltage through a
resistor.
Voltage Sense Input. This pin is connected directly to the VR output voltage of Loop #1 at the
load and should be routed differentially with VRTN.
Voltage Sense Return Input. This pin is connected directly to Loop#1 ground at the load and
should be routed differentially with VSEN.
Do Not Connect
I in. Input current signal that ranges from 0 to 1.25Vdc indicating a maximum input current of
62.5 Amps.
Temperature Sense Input Loop 1. An NTC network or the temperature reporting output from an
IR PowIRstage can be connected to this pin to measure temperature for VRHOT and OTP
shutdown. When connected to the IR PowIRstage’s temperature output; the scaled input voltage
to the controller needs to be at a gain of 4.88mV per degC and an offset of 0.365 Vdc so the
controller can correctly report temperature. Typically a 10kohm and 6.49kohm resistive divider is
used to accomplish the scaling between the power stage and the controller.
1.8V Decoupling. A 1F capacitor on this pin provides decoupling for the internal 1.8V supply.
Voltage Regulator Ready Output (Loop #1). Open-drain output that asserts high when the VR
has completed soft-start to Loop #1 boot voltage. Pull-up to an external voltage through a
resistor.
Enable Input for Loop #2. This pin may be configured as an Enable input for loop #2.
Power OK Input (AMD). An input that when low indicates to return to the Boot voltage and when
high indicates to use the SVI bus.
Catastrophic Fault Output Pin. This pin may be used as a Catastrophic Fault CMOS Output Pin
that is driven to VCC under output OVP, NVM CRC errors or a TSEN fault input.
Do Not Connect
Voltage Sense Input. This is used to detect and measure a valid input supply voltage (typically
4.5V-13.2V) to the VR.
Do Not Connect
Serial VID Address. If present, a resistor to ground sets the offset to the SVID address set in
NVM. If not, the value stored in NVM is used. Requires a 0.01µF to ground for noise filtering.
VDDIO Input (AMD). This pin provides the voltage to which the SVT line and the SVD
Acknowledge are driven high.
Serial VID ALERT# (INTEL). SVID ALERT# is pulled low by the controller to alert the CPU of
new IMVP8/VR12/VR12.5 Status. Pull-up to an external voltage through a resistor.
SVI Telemetry Output (AMD). Telemetry and VOTF information output by the IR35201
Serial VID Clock Input. Clock input driven by the CPU Master.
Serial VID Data I/O. Is a bi-directional serial line over which the CPU Master issues commands to
slave/s and receives data back.
VRHOT_ICRIT# Output. Active low alert pin that can be programmed to assert if temperature or
average load current exceeds user-definable thresholds. Pull-up to an external voltage through a
resistor.
5 www.irf.com | © 2016 International Rectifier
February 8, 2015 | V1.6
5 Page 
8+0/7+1/6+2 Dual Output Digital Multi-Phase Controller
IR35201
PARAMETER
Output Leakage
SYMBOL
CONDITIONS
Vpad = 0 to 3.6V
MIN TYP MAX UNIT
- - ±5 µA
Open-Drain Outputs – 20mA Drive
Output Low Voltage1
On Resistance1
VR_HOT_ICRIT#, SV_DIO, SV_ALERT#, PIN_ALERT#
I = 20mA
-
I = 20mA
7
- 0.26 V
9 13 Ω
Tri-State Leakage
Ileak Vpad = 0 to 3.6V
- - ±5 µA
PWM I/O
PWMx
Output Low Voltage (Tri-state mode)
I = -4mA
- - 0.4 V
Output High Voltage (Tri-State mode)
I =+4mA
2.9 -
-V
Tri-State Leakage
loop_x_pwm_en_ats = 0,
Vpad = 0 to Vcc
-
- ±1 µA
PWM Auto-Detect Inputs (when 3.3V Vcc is applied) – if enabled
Input Voltage High
0.7 -
-V
Input Voltage Low
- - 0.35 V
AMD SVI2 Bus
Tperiod (SVC Period)1
SVC
47.6 10,000 nSec
SVI2 SVC Frequency1
SVC
0.1 20.0 21.0 MHz
I2C/PMBus & Reporting
Bus Speed1
Normal
- 100
- kHz
Fast
- 400
- kHz
Maximum
- 1000
- kHz
Iout , Vout , Iin, Vin, Pin and Temperature
Filter Rate1
Iout Update Rate1
Vout Update Rate1
Vin & Temperature Update Rate1
Vin Range Reporting1
Selectable
(Selected Frequency applies
to all parameters)
With 14:1 divider
0.69, 1.39,
-
2.78, 5.55,
11.1, 22.2,
44.6, 89.5
- 250
- 35.7
- 35.7
- 0 to 13.2
-
-
-
-
-
Hz
kHz
kHz
kHz
V
Vin Accuracy Reporting
With 1% resistors
-2 - +2 %
Vin Resolution Reporting -PMBUS1
- 31.25
- mV
Vin Resolution Reporting –I2C1
Vout Range Reporting1
Vout Accuracy Reporting1
Vout Resolution Reporting-PMBUS1
Vout Resolution Reporting-I2C1
Iout Per Phase Range Reporting1
Iout Accuracy Reporting1
Loop1 Iout Resolution Reporting-PMBUS 1
Loop2 Iout Resolution Reporting-PMBUS 1
Loop1 Iout Resolution Reporting-I2C 1
Loop2 Iout Resolution Reporting-I2C 1
Loop1 Iin Resolution Reporting-PMBUS 1
No load-line
Vout < 2V
Vout < 4V
Maximum load, all phase
active (based on DCR,
NTC and # active phases)
*0.5A if >255.75A
- 125
- mV
- - 4V
±0.5 %
- 1.95
- mV
- 15.6
- mV
0 - 62 A
- ±2
-%
- 0.25*
- 0.25
-1
- 0.5
- 31.25
-A
-A
-A
-A
- mA
11 www.irf.com | © 2016 International Rectifier
February 8, 2015 | V1.6
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IR35201.PDF ] | |
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