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PDF CD4025BM Data sheet ( Hoja de datos )

Número de pieza CD4025BM
Descripción Buffered Triple 3-Input NAND/NOR Gate
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! CD4025BM Hoja de datos, Descripción, Manual

February 1988
CD4023BM CD4023BC
Buffered Triple 3-Input NAND Gate
CD4025BM CD4025BC
Buffered Triple 3-Input NOR Gate
General Description
These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and P-chan-
nel enhancement mode transistors They have equal source
and sink current capabilities and conform to standard B se-
ries output drive The devices also have buffered outputs
which improve transfer characteristics by providing very
high gain All inputs are protected against static discharge
with diodes to VDD and VSS
Features
Y Wide supply voltage range
3 0V to 15V
Y High noise immunity
Y Low power TTL
0 45 VDD (typ )
fan out of 2 driving 74L
compatibility
or 1 driving 74LS
Y 5V – 10V – 15V parametric ratings
Y Symmetrical output characteristics
Y Maximum input leakage 1 mA at 15V over full
temperature range
Connection Diagrams
CD4023BM CD4023BC
Dual-In-Line Package
CD4025BM CD4025BC
Dual-In-Line Package
Top View
TL F 5956 – 1
Order Number CD4023B or CD4025B
Top View
TL F 5956 – 2
C1995 National Semiconductor Corporation TL F 5956
RRD-B30M105 Printed in U S A

1 page




CD4025BM pdf
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4023BMJ CD4023BCJ CD4025BMJ or CD4025BCJ
NS Package Number J14A
5

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