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PDF BD37069FV-M Data sheet ( Hoja de datos )
| Número de pieza | BD37069FV-M | |
| Descripción | Sound Processor | |
| Fabricantes | ROHM Semiconductor | |
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Datasheet
Sound Processor for Car Audio
with Built-in High-Voltage Amplifier and
2nd Order Post Filter
BD37069FV-M
General Description
BD37069FV-M is a sound processor developed for car
audio with built-in selector of six stereo inputs and output
interfaced to ADC after adjusting signal level.
BD37069FV-M has a 6-channel volume circuit and
built-in 2nd order post filter which reduces the out-of
-band noise. The High-Voltage function is capable to
reach up to 5.2VRMS maximum output. Furthermore, the
IC is simple to design due to the built-in TDMA noise
reduction systems.
Key Specifications(Note2)
Total Harmonic Distortion:
0.003%(Typ)
Maximum Input Voltage:
Common Mode Rejection Ratio :
2.1VRMS(Typ)
55dB(Min)
Maximum Output Voltage:
Output Noise Voltage:
Residual Output Noise Voltage:
Ripple Rejection Ratio:
5.2VRMS(Typ)
23μVRMS(Typ)
10.5μVRMS(Typ)
-70dB (Typ)
Operating Temperature Range:
-40°C to +85°C
(Note2)These specifications are High-Voltage mode2.
Features
AEC-Q100 Qualified (Note1)
Built-in differential input selector that can select
single-ended / differential input
Reduce switching pop noise of input gain control due
to the built-in advanced switch circuit
Less out-of-band noise of DAC by built-in 2nd order
post filter
Built-in buffered ground isolation amplifier to achieve
high CMRR characteristics
Built-in TDMA noise reduction circuit reduces the
additional components for external filter
Available to output 5.2VRMS by High-Voltage function
(This device is possible to 3.2VRMS output by using
another High-Voltage mode, VCCH=11.5V)
Available to control by 3.3V / 5V for I2C-bus
controller
The input and output terminals are located together to
arrange the flow of signal in a same direction making
the PCB layout easier and PCB area smaller
(Note 1) Grade 3
Package
SSOP-B40
W(Typ) x D(Typ) x H(Max)
13.60mm x 7.80mm x 2.00mm
Applications
Car Audio and Other Audio Equipment
Typical Application Circuit
CD
USB
TUN
AUX
AUX
BT
A1
A2
B1
B2
CP1
CN
CP2
DP1
DN
DP2
EP1
EN
EP2
FP1
FN1
FN2
FP2
ADC
DSP
DAC
IG1 IG2 INF2 INF1 INR2 INR1
INS INC
Main Gain adjust Sub Gain adjust
Fader
boost ★
Fader
boost ★
2nd order
LPF
2nd order
LPF
BD37069FV-M
Fader
ATT★
Fader
ATT★
Level
Shift
Sub SEL
Level
Shift
OUTC
OUTS
Rear SEL
Front SEL
Fader
boost ★
Fader
boost★
2nd order
LPF
2nd order
LPF
Fader
boost ★
Fader
boost★
2nd order
LPF
2nd order
LPF
Fader
ATT★
Fader
ATT★
Fader
ATT★
Fader
ATT★
Level
Shift
OUTR1
Level OUTR2
Shift
★ Level
Shift
OUTF1
★ Level
Shift
OUTF2
Advanced Switch
MIN
Figure 1. Typical Application Circuit
NAVI
○Product structure：Silicon monolithic integrated circuit
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This product has no designed protection against radioactive rays
1/37
TSZ02201-0C2C0E100270-1-2
12. MAY. 2016 Rev.001
1 page  
BD37069FV-M
Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Rating
Unit
Power Supply Voltage
Input Voltage
Storage Temperature
VCCL
VCCH
VIN
TSTG
SCL, SDA
Other
10
18
GND-0.3 to +7
GND-0.3 to VCCL+0.3
-55 to +150
V
V
V
°C
Maximum Junction Temperature
TJMAX
+150
°C
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the
absolute maximum ratings.
Thermal Resistance(Note 1)
Parameter
Symbol
Thermal Resistance (Typ)
1s(Note 3)
2s2p(Note 4)
Unit
SSOP-B40
Junction to Ambient
θJA 103.6
58.8 °C/W
Junction to Top Characterization Parameter(Note 2)
ΨJT 17
10 °C/W
(Note 1)Based on JESD51-2A(Still-Air)
(Note 2)The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3)Using a PCB board based on JESD51-3.
(Note 4)Using a PCB board based on JESD51-7
Layer Number of
Measurement Board
Single
Material
FR-4
Board Size
114.3mm x 76.2mm x 1.6mmt
Top
Copper Pattern
Footprints and Traces
Thickness
70μm
.
Layer Number of
Measurement Board
4 Layers
Top
Copper Pattern
Footprints and Traces
Material
FR-4
Thickness
70μm
Board Size
114.3mm x 76.2mm x 1.6mmt
2 Internal Layers
Copper Pattern
Thickness
74.2mm x 74.2mm
35μm
Bottom
Copper Pattern
74.2mm x 74.2mm
Thickness
70μm
Recommended Operating Condition (Ta= -40°C to +85°C)
Parameter
Symbol
Min
Typ
Max Unit
Power Supply Voltage
VCCL
7.0
9
9.5 V
VCCH
VCCL
17
17.8 V
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/37
TSZ02201-0C2C0E100270-1-2
12. MAY. 2016 Rev.001
5 Page 
BD37069FV-M
I2C-bus CONTROL SIGNAL SPECIFICATION
(1) Electrical specifications and timing for bus lines and I/O stages
SDA
SCL
tBUF
tLOW
tHD;STA
T
tSP
tHD;STA
tHD;DAT
PS
tHIGH
tSU;DAT tSU;STA
T
Figure 12. Definition of Timing on the I2C-bus
tSU;STO
T
P
Table 1 Characteristics of the SDA and SCL bus lines for I2C-bus devices
Parameter
1 SCL Clock Frequency
2 Bus Free Time between STOP and START Condition
3
Hold Time (repeated) START condition.
After this period, the first clock pulse is generated
4 LOW Period of the SCL Clock
5 HIGH Period of the SCL Clock
6 Set-up Time for a Repeated START Condition
7 Data Hold Time
8 Data Set-up Time
9 Set-up Time for STOP Condition
All values referred to VIH min. and VIL max. Levels (see Table 2).
Table 2 Characteristics of the SDA and SCL I/O stages for I2C-bus devices
Parameter
10 LOW level input voltage: Fixed input levels
11 HIGH level input voltage: Fixed input levels
12 Pulse width of spikes, which must be suppressed by the input filter.
13
LOW level output voltage (open drain or open collector): At 3mA sink
current
14
Input current each I/O pin with an input voltage between 0.4V and 0.9
VDD max.
Symbol
fSCL
tBUF
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU; DAT
tSU;STO
Symbol
VIL
VIH
tSP
VOL1
II
Fast-mode I2C-bus
Min Max
0 400
1.3 －
0.6 －
1.3 －
0.6 －
0.6 －
0* －
100 －
0.6 －
Unit
kHz
μsec
μsec
μsec
μsec
μsec
μsec
nsec
μsec
Fast-mode I2C-bus
Min Max
-0.5 1
2.3 -
0 50
Unit
V
V
nsec
0 0.4 V
-10 10 μA
ｔHD;STA
2µsec
ｔHD;DAT
1µsec
ｔSU;DAT
1µsec
ｔSU;STO
2µsec
SCL
ｔBUF
4µsec
SDA
ｔLOW
3µsec
ｔHIGH
1µsec
SCL clock frequency:250kHz
Figure 13. I2C-bus data transmission timing
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
11/37
TSZ02201-0C2C0E100270-1-2
12. MAY. 2016 Rev.001
11 Page | ||
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| PDF Descargar | [ Datasheet BD37069FV-M.PDF ] | |
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