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PDF EN29LV800C Data sheet ( Hoja de datos )

Número de pieza EN29LV800C
Descripción 8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory
Fabricantes Eon Silicon Solution 
Logotipo Eon Silicon Solution Logotipo



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EN29LV800C
Purpose
Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on
ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the
compositions of the ICs. Eon is still keeping the promise of quality for all the products with the
same as that of Eon delivered before. Please be advised with the change and appreciate your
kindly cooperation and fully support Eon’s product family.
Eon products’ New Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX
Lot Number: XXXXX
Date Code: XXXXX
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as an Eon product. Any
changes that have been made are the result of normal data sheet improvement and are noted in
the document revision summary, where supported. Future routine revisions will occur when
appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Eon continues to support existing part numbers beginning with “Eon” and “cFeon” top marking. To
order these products, during the transition please specify “Eon top marking” or “cFeon top marking”
on your purchasing orders.
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
© 2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2011/10/26
www.eonssi.com

1 page




EN29LV800C pdf
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EN29LV800C
TABLE 2A. TOP BOOT BLOCK SECTOR ARCHITECTURE
ADDRESS RANGE
(X16)
(X8)
SECTOR
SIZE
(Kbytes / A18 A17 A16 A15 A14 A13 A12
Kwords)
7E000h-7FFFFh FC000h-FFFFFh
16/8
111111X
7D000h-7DFFFh FA000h-FBFFFh 8/4 1 1 1 1 1 0 1
7C000h-7CFFFh F8000h-F9FFFh 8/4 1 1 1 1 1 0 0
78000h-7BFFFh F0000h – F7FFFh 32/16
1 1 1 1 0XX
70000h-77FFFh E0000h - EFFFFh 64/32
1 1 1 0XXX
68000h-6FFFFh D0000h - DFFFFh 64/32
1 1 0 1XXX
60000h-6FFFFh C0000h - CFFFFh 64/32
1 1 0 0XXX
58000h-5FFFFh B0000h - BFFFFh 64/32
1 0 1 1XXX
50000h-57FFFh A0000h - AFFFFh 64/32
1 0 1 0XXX
48000h-4FFFFh 90000h - 9FFFFh 64/32
1 0 0 1XXX
40000h-47FFFh 80000h - 8FFFFh 64/32
1 0 0 0XXX
38000h-3FFFFh 70000h - 7FFFFh 64/32
0 1 1 1XXX
30000h-37FFFh 60000h - 6FFFFh 64/32
0 1 1 0XXX
28000h-2FFFFh 50000h – 5FFFFh 64/32
0 1 0 1XXX
20000h-27FFFh 40000h – 4FFFFh 64/32
0 1 0 0XXX
18000h-1FFFFh 30000h – 3FFFFh 64/32
0 0 1 1XXX
10000h-17FFFh 20000h - 2FFFFh 64/32
0 0 1 0XXX
08000h-0FFFFh 10000h - 1FFFFh 64/32
0 0 0 1XXX
00000h-07FFFh 00000h - 0FFFFh 64/32
0 0 0 0XXX
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
© 2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2011/10/26
www.eonssi.com

5 Page





EN29LV800C arduino
EN29LV800C
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by false system level signals during Vcc power up and power down transitions, or
from system noise.
Low VCC Write Inhibit
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc
power up and power down. The command register and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must
provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than
VLKO.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write
cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all
logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with
CE# = VIL, WE# = VIL and OE# = VIH, the device will not accept commands on the rising edge of WE#.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
11
© 2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2011/10/26
www.eonssi.com

11 Page







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