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PDF CD4019BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4019BMS | |
| Descripción | CMOS Quad AND/OR Select Gate | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4019BMS
November 1994
CMOS Quad AND/OR Select Gate
Features
Pinout
• High Voltage Type (20V Rating)
• Medium Speed Operation tPHL = tPLH = 60ns (typ.) at
CL = 50pF, VDD = 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
• Maximum Input Current of 1µa at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25oC
B4 1
A3 2
B3 3
A2 4
B2 5
A1 6
B1 7
VSS 8
CD4019BMS
TOP VIEW
16 VDD
15 A4
14 Kb
13 D4 = A4 Ka + B4 Kb
12 D3 = A3 Ka + B3 Kb
11 D2 = A2 Ka + B2 Kb
10 D1 = A1 Ka + B1 Kb
9 Ka
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Applications
Functional Diagram
Ka Kb
9 14
VDD
16
• And/Or Select Gating
• Shift-Right/Shift-Left Registers
• True/Complement Selection
• AND/OR/Exclusive-OR Selection
Description
CD4019BMS types consist of four AND/OR select gate con-
figurations, each consisting of two 2-input AND gates driving
a single 2-input OR gate. Selection is accomplished by con-
trol bits Ka and Kb. In addition to selection of either channel
A or channel B information, the control bits can be applied
simultaneously to accomplish the logical A + B function.
15
A4
B4 1
A3 2
B3 3
A2 4
B2 5
6
A1
7
B1
13
D4
12 D3
D4 = (A4 Ka) + (B4 Kb) 11 D2
10 D1
8
VSS
The CD4019BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1E
H3X
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-307
File Number 3299
1 page  
Specifications CD4019BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
Static Burn-In 1
Note 1
OPEN
10 -13
GROUND
1 - 9, 14, 15
VDD
16
9V ± -0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 2
Note 1
10 -13
8 1 - 7, 9, 14 - 16
Dynamic Burn-
In Note 1
-
8
16 10 - 13
- 1 - 7, 9, 14, 15
Irradiation
Note 2
10 -13
8 1 - 7, 9, 14 - 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagram
*Ka 9
VDD = 16
VSS - 8
*Kb 14
*A4 15
*B4 1
VDD *A3 2
*B3 3
*A2 4
VSS *B2
*INPUTS PROTECTED
BY CMOS PROTECTION
*A1
NETWORK
*B1
5
6
7
TO 3 MORE
SIMILAR
CIRCUITS
13 D4
12 D3
11 D2
10
D1
TRUTH TABLE
Ka Kb An Bn
101X
100X
01X1
01X0
0 0XX
1100
1101
1110
1111
X = Don’t Care Case
Dn
1
0
1
0
0
0
1
1
1
FIGURE 1. CD4019BMS LOGIC DIAGRAM
7-311
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CD4019BMS.PDF ] | |
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