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PDF S-24C04A Data sheet ( Hoja de datos )
| Número de pieza | S-24C04A | |
| Descripción | CMOS 2-WIRE SERIAL EEPROM | |
| Fabricantes | Seiko | |
| Logotipo |  |
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Rev. 2.2_30
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
The S-24C0XA is a series of 2-wired, low power 1K/2K/4K-bit EEPROMs
with a wide operating range. They are organized as 128-word × 8-bit,
256-word × 8-bit, and 512-word × 8-bit, respectively. Each is capable of
page write, and sequential read.
The time for byte write and page write is the same, i. e., 1 msec. (max.)
during operation at 5 V ± 10%.
Features
• Low power consumption
Standby: 1.0 µA Max.
Operating: 0.4 mA Max.
0.3 mA Max.
(VCC=5.5 V)
(VCC=5.5 V)
(VCC=3.3 V)
• Wide operating voltage range
Write: 2.5 to 5.5 V
Read: 1.8 to 5.5 V
• Page write
8 bytes (S-24C01A, S-24C02A)
16 bytes (S-24C04A)
Package
y 8-pin DIP
y 8-pin SOP
(PKG drawing code : DP008-A,DP008-C)
(PKG drawing code : FJ008-D,FJ008-E)
• Endurance:
• Data retention:
• Write protection:
• S-24C01A:
• S-24C02A:
• S-24C04A:
106 cycles/word
10 years
S-24C02A, S-24C04A
1 kbits
2 kbits
4 kbits
Pin Assignment
8-pin DIP
Top view
8-pin SOP
Top view
A0 1
8
A1 2
7
A2 3
6
GND 4
5
S-24C01ADPx-uu
S-24C02ADPx-uu
S-24C04ADPx-uu
Pin Functions
VCC
TEST/WP
SCL
SDA
Figure 1
Table 1
A0
A1
A2
GND
1
2
3
4
8 VCC
7 TEST/WP
6 SCL
5 SDA
S-24C01AFJA-zz-uuw
S-24C02AFJA-zz-uuw
S-24C04AFJA-zz-uuw
* Lower-case letters x, uu, zz and w differ
depending on the packing form.
See Ordering Information and Dimensions.
Name
A0
A1
A2
GND
SDA
SCL
TEST/WP
VCC
Pin Number
DIP SOP
11
22
33
44
55
66
77
88
Function
Address input (no connection in the S-24C04A*)
Address input
Address input
Ground
Serial data input/output
Serial clock input
TEST pin (S-24C01A): Connected to GND.
WP (Write Protection) pin (S-24C02A, S-24C04A):
* Connected to Vcc:
Protection valid
* Connected to GND: Protection invalid
Power supply
* When in use, connect to
GND or Vcc.
Seiko Instruments Inc.
1
1 page  
Rev. 2.2_30
AC Electrical Characteristics
Table 8 Measurement Conditions
Input pulse voltage
Input pulse rising/falling time
Output judgment voltage
Output load
0.1×VCC to 0.9×VCC
20 ns
0.5×VCC
100 pF+ Pullup resistance 1.0 kΩ
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
VCC
SDA
R=1.0k
C=100pF
Figure 3 Output Load Circuit
Parameter
SCL clock frequency
SCL clock time "L"
SCL clock time"H"
SDA output delay time
SDA output hold time
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
SCL · SDA rising time
SCL · SDA falling time
Bus release time
Noise suppression time
Table 9
Symbol
fSCL
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tBUF
tI
VCC=1.8V to 5.5V
Min. Typ. Max.
0 — 100
4.7 — —
4.0 — —
0.3 — 3.5
0.3 — —
4.7 — —
4.0 — —
50 — —
0 ——
4.7 — —
— — 1.0
— — 0.3
4.7 — —
— — 100
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ns
SCL
SDA IN
SDA OUT
tSU.STA
tF tHIGH
tLOW
tHD.STA
tHD.DAT
tSU.DAT
invalid
tAA
valid
tDH
Figure 4 Bus Timing
tR
tSU.STO
tBUF
Seiko Instruments Inc.
5
5 Page 
Rev. 2.2_30
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
7. Read
7.1 Current Address Read
The EEPROM is capable of storing the last accessed memory address during both writing and
reading. The memory address is stored as long as the power voltage is more than the retention
voltage VAH.
Accordingly, when the master device recognizes the position of the address pointer inside the
EEPROM, data can be read from the memory address of the current address pointer without
assigning a word address. This is called "Current Address Read."
"Current Address Read" is explained for when the address counter inside the EEPROM is an "n"
address.
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code
"1," following the start condition signal, it outputs the acknowledgment signal. However, in the S-
24C04A, page address P0 becomes invalid, and the memory address of the current address pointer
becomes valid.
Next, 8-bit length data at an "n" address is output from the EEPROM, in synchronization with the
SCL clock.
The address counter is incremented at the falling edge of the SCL clock by which the 8th bit of data
is output, and the address counter goes to address n+1.
The master device does not output the acknowledgment signal and transmits the stop condition
signal to finish reading.
S
TR
AE
R DEVICE A
T ADDRESS D
NO ACK from
Master Device
SDA LINE
1 0 1 0 A2 A1 A0 1 D7 D6 D5 D4 D3 D2 D1 D0
M
S
LR A
S/ C
DATA
B BW K
S
T
O
P
(A0 is P0 in the S-24C04A)
ADR INC
Figure 12 Current Address Read
For recognition of the address pointer inside the EEPROM, take into consideration the following:
The memory address counter inside the EEPROM is automatically incremented for every falling
edge of the SCL clock by which the 8th bit of data is output during the time of reading. During the
time of writing, upper bits of the memory address (upper 5 bits of the word address in the S-24C01A
and S-24C02A; upper 4 bits of the word address and page address P0 in the S-24C04A) are left
unchanged and are not incremented.
Seiko Instruments Inc.
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet S-24C04A.PDF ] | |
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