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PDF KSZ9021RN Data sheet ( Hoja de datos )

Número de pieza KSZ9021RN
Descripción Gigabit Ethernet Transceiver
Fabricantes Micrel Semiconductor 
Logotipo Micrel Semiconductor Logotipo



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KSZ9021RL/RN
Gigabit Ethernet Transceiver
with RGMII Support
Revision 1.2
General Description
The KSZ9021RL is a completely integrated triple speed
(10Base-T/100Base-TX/1000Base-T) Ethernet Physical
Layer Transceiver for transmission and reception of data
over standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ9021RL provides the Reduced Gigabit Media
Independent Interface (RGMII) for direct connection to
RGMII MACs in Gigabit Ethernet Processors and Switches
for data transfer at 10/100/1000Mbps speed.
The KSZ9021RL reduces board cost and simplifies board
layout by using on-chip termination resistors for the four
differential pairs and by integrating a LDO controller to
drive a low cost MOSFET to supply the 1.2V core.
The KSZ9021RL provides diagnostic features to facilitate
system bring-up and debugging in production testing and
in product deployment. Parametric NAND tree support
enables fault detection between KSZ9021 I/Os and board.
Micrel LinkMD® TDR-based cable diagnostics permit
identification of faulty copper cabling. Remote and local
loopback functions provide verification of analog and
digital data paths.
The KSZ9021RL is available in a 64-pin, lead-free E-LQFP
package, and is offered as the KSZ9021RN in the smaller
48-pin QFN package (See Ordering Information).
Features
Single-chip 10/100/1000Mbps IEEE 802.3 compliant
Ethernet Transceiver
RGMII interface compliant to RGMII Version 1.3
RGMII I/Os with 3.3V/2.5V tolerant and programmable
timings to adjust and correct delays on both Tx and Rx
paths
Auto-negotiation to automatically select the highest link
up speed (10/100/100Mbps) and duplex (half/full)
On-chip termination resistors for the differential pairs
On-chip LDO controller to support single 3.3V supply
operation – requires only external FET to generate 1.2V
for the core
Jumbo frame support up to 16KB
125MHz Reference Clock Output
Programmable LED outputs for link, activity and speed
Baseline Wander Correction
LinkMD® TDR-based cable diagnostics for identification
of faulty copper cabling
Parametric NAND Tree support for fault detection
between chip I/Os and board.
Loopback modes for diagnostics
____________________________________________________________________________________________________________
Functional Diagram
10/100/1000 Mbps
RGMII
Ethernet MAC
RGMII
MDC / MDIO
Management
KSZ9021RL/RN
VIN
3.3VA
LDO
Controller
VOUT
1.2V (for core voltages)
RJ-45
Connector
Media Types:
10Base-T
100Base-TX
1000Base-T
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
February 13, 2014
Revision 1.2

1 page




KSZ9021RN pdf
Micrel, Inc.
KSZ9021RL/RN
Register Description ........................................................................................................................................................... 36
IEEE Defined Registers .................................................................................................................................................... 36
Vendor Specific Registers ................................................................................................................................................ 43
Extended Registers .......................................................................................................................................................... 45
Absolute Maximum Ratings ............................................................................................................................................... 48
Operating Ratings ............................................................................................................................................................... 48
Electrical Characteristics ................................................................................................................................................... 48
Timing Diagrams ................................................................................................................................................................. 50
RGMII Timing.................................................................................................................................................................... 50
Auto-Negotiation Timing ................................................................................................................................................... 51
MDC/MDIO Timing ........................................................................................................................................................... 52
Reset Timing..................................................................................................................................................................... 53
Reset Circuit ........................................................................................................................................................................ 53
Reference Circuits – LED Strap-in Pins............................................................................................................................ 54
Reference Clock – Connection and Selection.................................................................................................................. 55
Magnetics Specification ..................................................................................................................................................... 55
Package Information ........................................................................................................................................................... 56
February 13, 2014
5 Revision 1.2

5 Page





KSZ9021RN arduino
Micrel, Inc.
Pin Number
21
Pin Name
LED1 /
PHYAD0
KSZ9021RL/RN
Type(1)
I/O
Pin Function
LED Output: Programmable LED1 Output /
Config Mode: The pull-up/pull-down value is latched as PHYAD[0] during
power-up/reset. See “Strapping Options” section for details.
The LED1 pin is programmed by the LED_MODE strapping option (pin 55), and is
defined as follows.
Single LED Mode
Activity
No Activity
Activity (RX, TX)
Pin State
H
Toggle
LED Definition
OFF
Blinking
Tri-color Dual LED Mode
Link / Activity
Link off
1000 Link / No Activity
1000 Link / Activity (RX, TX)
100 Link / No Activity
100 Link / Activity (RX, TX)
10 Link / No Activity
10 Link / Activity (RX, TX)
Pin State
LED2 LED1
HH
LH
Toggle H
HL
H Toggle
LL
Toggle Toggle
LED Definition
LED2 LED1
OFF OFF
ON OFF
Blinking OFF
OFF
ON
OFF Blinking
ON ON
Blinking Blinking
For Tri-color Dual LED Mode, LED1 works in conjunction with LED2 (pin 19) to
indicate 10 Mbps Link and Activity.
22
DVDDL
P 1.2V digital VDD
23
VSS
Gnd Digital ground
24
TXD0
I RGMII Mode: RGMII TD0 (Transmit Data 0) Input
25
TXD1
I RGMII Mode: RGMII TD1 (Transmit Data 1) Input
26
TXD2
I RGMII Mode: RGMII TD2 (Transmit Data 2) Input
27
TXD3
I RGMII Mode: RGMII TD3 (Transmit Data 3) Input
28
VSS
Gnd Digital ground
29
DVDDL
P 1.2V digital VDD
30
DVDDH
P 3.3V/2.5V digital VDD
31
TX_ER
I RGMII Mode: This pin is not used and should be left as a no connect.
32
GTX_CLK
I RGMII Mode: RGMII TXC (Transmit Reference Clock) Input
33
TX_EN
I RGMII Mode: RGMII TX_CTL (Transmit Control) Input
34
VSS
Gnd Digital ground
35
DVDDL
P 1.2V digital VDD
February 13, 2014
11 Revision 1.2

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