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PDF CD40182BMS Data sheet ( Hoja de datos )

Número de pieza CD40182BMS
Descripción CMOS Look-Ahead Carry Generator
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! CD40182BMS Hoja de datos, Descripción, Manual

CD40182BMS
December 1992
CMOS Look-Ahead Carry Generator
Features
Description
• High Voltage Type (20V Rating)
• Generates High-Speed Carry Across Four Adders or
Adder Groups
• High-Speed Operation
- tPHL, tPLH =100 ns (typ) at VDD = 10V
• Cascadable for Fast Carries Over N Bits
• Designed for Use with CD40181BMS ALU
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
The CD40182BMS is a high-speed look-ahead carry gener-
ator capable of anticipating a carry across four binary adders
or groups of adders. The CD40182BMS is cascadable to
perform full look-ahead across n-bit adders. Carry, propa-
gate-carry, and generate-carry functions are provided as
enumerated in the terminal designation below.
The CD40182BMS, when used in conjuction with the
CD40181BMS arithmetic logic unit (ALU), provides full high-
speed look-ahead carry capability for up to n-bit words. Each
CD40182BMS generates the look-ahead (anticipated carry)
across a group of four ALU’s. In addition, other
CD40182BMS’s may be employed to anticipate the carry
across sections of four look-ahead blocks up to n-bits. Carry
inputs and outputs of the CD40181BMS are active-high
logic, and carry-generate (G) and carry-propagate (P) out-
puts are active-low. Therefore the inputs and outputs of the
CD40182BMS are compatible.
The CD40182BMS is supplied in these 16-lead outline
packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4V
H1E
H6P
The CD40182BMS is similar to industry type MC14582.
Applications
• High-Speed Parallel Arithmetric Units
• Multi-Level Look-Ahead Carry Generation for Long
Word Lengths
Pinout
CD40182BMS
TOP VIEW
G1 1
P1 2
G0 3
P0 4
G3 5
P3 6
P7
VSS 8
16 VDD
15 P2
14 G2
13 Cn
12 Cn + x
11 Cn + y
10 G
9 Cn + z
Functional Diagram
3
G0
1
G1
G 14
G2
5
G3
4
P0
2
P1
P 15
P2
6
P3
VDD = 16
VSS = 8
Cn 13
12
Cn + x
11
Cn + y
9
Cn + z
7
P
10
G
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1410
File Number 3362

1 page




CD40182BMS pdf
Specifications CD40182BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1
(Note 1)
OPEN
7, 9 - 12
GROUND
1 - 6, 8, 13 - 15
VDD
16
9V ± -0.5V
50kHz
25kHz
Static Burn-In 2
(Note 1)
7, 9 - 12
8 1 - 6, 13 - 16
Dynamic Burn-
In (Note 1)
-
8
16
7, 9 - 12
1 - 6, 14, 15
13
Irradiation
(Note 2)
7, 9 - 12
8 1 - 6, 13 - 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
TABLE 9. TERMINAL DESIGNATIONS
DESIGNATION
TERM.
FUNCTION
G0, G1, G2, G3
3, 1, 14, 5
Active-Low
Carry-Generate
Inputs
P0, P1, P2, P3
4, 2, 15, 6
Active-Low
Carry-Propagate
Inputs
Cn 13 Active-High
Carry Input
Cn + x, Cn + y, Cn + z
12, 11, 9
Active-High
Carry Outputs
7-1414

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