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PDF PALCE16V8 Data sheet ( Hoja de datos )
| Número de pieza | PALCE16V8 | |
| Descripción | EE CMOS 20-Pin Universal Programmable Array Logic | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-10/15/25, Q-20/25
PALCE16V8 Family
EE CMOS 20-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s Pin and function compatible with all 20-pin
GAL devices
s Electrically erasable CMOS technology
provides reconfigurable logic and full
testability
s High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
s Direct plug-in replacement for the PAL16R8
series and most of the PAL10H8 series
s Outputs programmable as registered or
combinatorial in any combination
s Peripheral Component Interconnect (PCI)
compliant
s Programmable output polarity
s Programmable enable/disable control
s Preloadable output registers for testability
s Automatic register reset on power up
s Cost-effective 20-pin plastic DIP, PLCC, and
SOIC packages
s Extensive third-party software and programmer
support through FusionPLD partners
s Fully tested for 100% programming and
functional yields and high reliability
s 5 ns version utilizes a split leadframe for
improved performance
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. It is functionally compatible with all 20-pin
GAL devices. The macrocells provide a universal device
architecture. The PALCE16V8 will directly replace the
PAL16R8 and PAL10H8 series devices, with the excep-
tion of the PAL16C1.
The PALCE16V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased
electrically.
The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
feeds the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial with an active-
high or active-low output. The output configuration is
determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
AMD’s FusionPLD program allows PALCE16V8 de-
signs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring that third-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
2-36
Publication# 16493 Rev. D Amendment /0
Issue Date: February 1996
1 page  
AMD
Configuration Options
Each macrocell can be configured as one of the follow-
ing: registered output, combinatorial output, combinato-
rial I/O, or dedicated input. In the registered output
configuration, the output buffer is enabled by the OE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, it is always disabled. With
the exception of MC0 and MC7, a macrocell configured
as a dedicated input derives the input signal from an ad-
jacent I/O. MC0 derives its input from pin 11 (OE) and
MC7 from pin 1 (CLK).
The macrocell configurations are controlled by the con-
figuration control word. It contains 2 global bits (SG0
and SG1) and 16 local bits (SL00 through SL07 and SL10
through SL17). SG0 determines whether registers will
be allowed. SG1 determines whether the PALCE16V8
will emulate a PAL16R8 family or a PAL10H8 family de-
vice. Within each macrocell, SL0x, in conjunction with
SG1, selects the configuration of the macrocell, and
SL1x sets the output as either active low or active high
for the individual macrocell.
The configuration bits work by acting as control inputs
for the multiplexers in the macrocell. There are four mul-
tiplexers: a product term input, an enable select, an out-
put select, and a feedback select multiplexer. SG1 and
SL0x are the control signals for all four multiplexers. In
MC0 and MC7, SG0 replaces SG1 on the feedback mul-
tiplexer. This accommodates CLK being the adjacent
pin for MC7 and OE the adjacent pin for MC0.
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0x =
0. There is only one registered configuration. All eight
product terms are available as inputs to the OR gate.
Data polarity is determined by SL1x. The flip-flop is
loaded on the LOW-to-HIGH transition of CLK. The
feedback path is from Q on the register. The output
buffer is enabled by OE.
Combinatorial Configurations
The PALCE16V8 has three combinatorial output con-
figurations: dedicated output in a non-registered device,
I/O in a non-registered device and I/O in a registered
device.
Dedicated Output in a Non-Registered
Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0x =
0. All eight product terms are available to the OR gate.
Although the macrocell is a dedicated output, the feed-
back is used, with the exception of pins 15 and 16. Pins
15 and 16 do not use feedback in this mode. Because
CLK and OE are not used in a non-registered device,
pins 1 and 11 are available as input signals. Pin 1 will
use the feedback path of MC7 and pin 11 will use the
feedback path of MC0.
Combinatorial I/O in a Non-Registered
Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0x =
1. Only seven product terms are available to the OR
gate. The eighth product term is used to enable the out-
put buffer. The signal at the I/O pin is fed back to the
AND array via the feedback multiplexer. This allows the
pin to be used as an input.
Because CLK and OE are not used in a non-registered
device, pins 1 and 11 are available as inputs. Pin 1 will
use the feedback path of MC7 and pin 11 will use the
feedback path of MC0.
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0x =
1. Only seven product terms are available to the OR
gate. The eighth product term is used as the output
enable. The feedback signal is the corresponding I/O
signal.
Dedicated Input Configuration
The control bit settings are SG0 = 1, SG1 = 0 and SL0x =
1. The output buffer is disabled. Except for MC0 and MC7
the feedback signal is an adjacent I/O. For MC0 and MC7
the feedback signals are pins 1 and 11. These configu-
rations are summarized in Table 1 and illustrated in
Figure 2.
Table 1. Macrocell Configuration
SG0 SG1 SL0X Cell Configuration Devices Emulated
Device Uses Registers
0 1 0 Registered Output PAL16R8, 16R6,
16R4
0 1 1 Combinatorial I/O PAL16R6, 16R4
Device Uses No Registers
1 0 0 Combinatorial
PAL10H8, 12H6,
Output
14H4, 16H2, 10L8,
12L6, 14L4, 16L2
1 0 1 Input
PAL12H6, 14H4,
16H2, 12L6, 14L4,
16L2
1 1 1 Combinatorial I/O PAL16L8
Programmable Output Polarity
The polarity of each macrocell can be active-high or ac-
tive-low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Selection is through a programmable bit SL1x which
controls an exclusive-OR gate at the output of the AND/
OR logic. The output is active high if SL1x is 1 and active
low if SL1x is 0.
2-40
PALCE16V8 Family
5 Page 
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Descriptions
Test Conditions
Typ Unit
CIN Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C,
5 pF
COUT
Output Capacitance
VOUT = 2.0 V
f = 1 MHz
8 pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
tPD
tS
tH
tCO
tSKEWR
tWL
tWH
fMAX
tPZX
tPXZ
tEA
tER
Parameter Description
Input or Feedback to Combinatorial Output
Setup Time from Input or Feedback to Clock
Hold Time
Clock to Output
Skew Between Registered Outputs (Note 4)
Clock Width
LOW
HIGH
Maximum
Frequency
(Note 3)
External Feedback
Internal Feedback (fCNT),
No Feedback
OE to Output Enable
OE to Output Disable
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
1/(tS+tCO)
1/(tS+tCF) (Note 6)
1/(tWH+tWL)
Min
(Note 5)
1
3
0
1
3
3
142.8
166
166
1
1
2
2
Max
5
4
1
6
5
6
5
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading.
5. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improve-
ments may alter these values therefore, minimum values are recommended for simulation purposes only.
6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
2-46
PALCE16V8H-5 (Com’l)
11 Page | ||
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| PDF Descargar | [ Datasheet PALCE16V8.PDF ] | |
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