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PDF VIPer31SP Data sheet ( Hoja de datos )
| Número de pieza | VIPer31SP | |
| Descripción | BATTERY CHARGER PRIMARY IC | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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VIPer31SP
BATTERY CHARGER PRIMARY I.C.
TYPE
VIPer31SP
VDSS
600 V
In RDS(on)
1 A 6.5 Ω
ADVANCE DATA
10
FEATURE
s RECTANGULAR CHARACTERISTIC,
WITHOUT OPTOCOUPLER
s INTERNALLY TRIMMED CURRENT
REFERENCE
s FIXED SWITCHING FREQUENCY,
ADJUSTABLE UP TO 150 KHZ
s AUXILIARY VOLTAGE REGULATOR
s SOFT START AND SHUT DOWN CONTROL
s AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
”BLUE ANGEL” NORM (<1W TOTAL POWER
CONSUMPTION)
s UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
s INTEGRATED START UP SUPPLY
s AVALANCHE RUGGED
s OVERVOLTAGE PROTECTION
s OVERTEMPERATURE PROTECTION
s CYCLE BY CYCLE CURRENT LIMITATION
s DEMAGNETISATION CONTROL
1
Power SO-10
DESCRIPTION
VIPer31SP combines on the same silicon chip a
PWM control dedicated to output current
regulation together with an optimised high voltage
avalanche rugged vertical power MOSFET
(600V/1A). Typical applications cover battery
chargers with constant current and constant
voltage output characteristics, without any
optocoupler between primary and secondary
sections. Typical output power capability is 15 W
in wide range condition and 30 W in single range
or with doubler configuration. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in no load
condition with an input power as low as 1W. This
feature insures the compliance towards ”Blue
Angel” norm and other similar ones.
BLOCK DIAGRAM
VCC
FB
COMP
OSC
ON/OFF
UVLO
LOGIC
2.6 V
-
+
29 V
+
-
OVERTEMP.
DETECTOR
10 V
REGULATOR
-+
OSCILLATOR
R1
R2 R3
FF Q
R4 PWM
LATCH
-+
CURRENT
REGULATION
200 ns
BLANKING
DRAIN
+
- 1.5 A
January 1998
VDD
GND
CREF
CSENSE
DSENSE
SOURCE
SC12000
1/16
1 page  
VIPer31SP
ELECTRICAL CHARACTERISTICS (continued)
ERROR AMPLIFIER SECTION
Symb ol
P a ram et er
VREF Reference Voltage
∆VREF
GBW
Temperaure Variation
Unity G ain Bandwidth
A VOL
Open Loop Voltage
Gain
IFB Input Bias Current
VCOMP LO Output Low Level
VCOMP HI Output High Level
ICOMP LO Output Low Current
Capability
ICOMP HI Output High Current
Capability
Test Conditions
ICOMP = 0 mA
TJ = 25 oC
(see fig. 4)
(see fig. 4)
VFB = 5 V
ICOMP = -100 µA
ICOMP = 100 µA
VCOMP = 5 V
VCOMP = 5 V
VFB = 5 V
VF B = 0 V
VFB = 5 V
VFB = 0 V
CURRENT REGULATION SECTION
Symb ol
P a ram et er
VREG Reference Voltage
td Current Sense Delay
to Turn-off
VDSENSEth Demagnetization
Detector Threshold
V o lt a ge
VDSENSEcl Demagnetization
Detector Clamping
V o lt a ge
Test Conditions
(see fig. 5)
(See fig 1)
(see fig. 6)
IDSENSE = 10 mA
(see fig. 6)
PROTECTION SECTION
Symb ol
IDl im
tb
VCClim
VC Ch y s t
TSD
TSDhyst
P a ram et er
Peak Drain Current
Li mit at i on
Current Limitation
Blanking Time
VCC Overvolt age
Threshold
VCC Overvolt age
Hy s t e re s is
Thermal Shutdown
Temperature
Thermal Shutdown
Hy s t e re s is
RS = 0
Test Conditions
(see fig. 9)
RS = 0
VFB = 0 V
(see fig. 9)
(see fig. 7)
VFB = 0 V
(see fig. 8)
(see fig. 7)
(see fig. 8)
Min.
TBD
TBD
Typ .
2.6
TBD
400
50
M a x.
TBD
TBD
Unit
V
%
KHz
dB
2.5 5 µA
1V
9V
3.5 mA
-3.5 mA
Min.
320
Typ .
350
M a x.
380
350
Unit
mV
ns
2.6 V
6V
Min.
1
Typ .
M a x.
2.5
Unit
A
1.2 µs
26 35 V
2
150
TBD
V
oC
oC
5/16
5 Page 
VIPer31SP
An external resistance R1 is needed to withstand
the negative voltage generated by the winding. As
long as the transformer is delivering some energy
on secondary side, the negated EOD signal
remains in the high state and the mosfet switch Q
is on. The duration of this state is noted tonsec
and corresponds to the time where the secondary
current is flowing through D1. For details about
the demagnetisation function, refer to figure 6.
The average output current can be expressed as:
IOUT
=
IS
2
X
tONSEC
TSW
Where :
(1)
IS is the peak secondary current.
tONSEC is the conduction time on secondary side.
TSW is the switching period.
Taking into account the transformer ratio n
between primary and secondaryside, IS can also
be expressed versus primary peak current IP :
IS = n x IP
(2)
The value of the capacitor C is sufficiently high to
consider the voltage Uc as constant. This
capacitor is submitted to a charging current and
discharging current at the rhythm of the switching
frequency. As these currents are in the range of a
few mA (Iref is typically 1 mA), a 470 nF is a
suited value for a switching frequency of 60 kHz.
In steady state, it can be written that the charge is
equal to the discharge :
IREF
x (TSW
−
t
ONSEC)
=
(
UC
R
−
IREF
)
x
t
ONSEC
It comes :
UC
=R
x
IREF
x
TSW
tONSEC
(3)
As UC can be considered as a constant voltage,
can be also expressed as :
IP
=
UC
RS
(4)
Combining (1), (2), (3) and (4) :
IOUT
=
n
2
x
R
x IREF
RS
This last expression shows that the average
output current doesn’t depend any more neither
on the output voltage, nor on the duty cycle, nor
on the input voltage. The only parameters which
are setting its value are :
The transformer ratio n.
The sense resistor value RS
The product R x IREF
This product corresponds to a voltage which is
noted Vreg in the specification tables. Figure 5
shows the test fixture for measuring it : The
DSENSE pin is held in the high state (In fact, it is
left open, as an internal pull up current source is
internally connected on this pin) and the mosfet
switch Q is always in the high state. In this case,
the voltage on the CREF pin establishes at
R x IREF .
Note that the oscillator must be running for the
demagnetisation block to sample correctly the
DSENSE pin.
As Vreg has a typical value of 350 mV, the output
current can be finally written as :
IOUT
=
n
x
0.175
RS
A sense resistor of 1.3 Ω with a transformer ratio
of 6 gives a typical output current of about 800
mA.
The schematics of figure 10 shows a
compensation on the CSENSE pin with the two
resistances R5 and R7. These resistances are
connected on the Vin input voltage and are
providing an offset on the current sense pin. The
higher is the input voltage, and the higher is this
offset current. The purpose of this compensation
is to cancel the effect of the current control
propagation time td, which induces an extra
current on top of the theoretical peak current Ip
given by (4).
The output current obtained with this
compensation can be seen on figure 11. The
typical ”flatness” is about +/-2.5 %, including the
input voltage variation from 100 VDC to 400 VDC.
If less accuracy is needed, these two resistances
can be omitted.
CONSTANT VOLTAGE OPERATION
An another part of the circuit is in charge of the
regulation of the output voltage, and generates
the vertical characteristic of figure 11. It consists
of a primary feedback regulation, with a
conventional voltage mode control : An
operational amplifier with an internal voltage
reference of 2.6 V is configured in error amplifier
and defines the duty cycle of the power mosfet
switch by comparison with the oscillator sawtooth
(See block diagram on page 1).
As it is a primary feedback, the accuracy of the
output voltage depends closely on the
transformer coupling quality. This is especially
11/16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet VIPer31SP.PDF ] | |
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