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PDF S-57M1 Data sheet ( Hoja de datos )
| Número de pieza | S-57M1 | |
| Descripción | HIGH-SPEED BIPOLAR HALL EFFECT LATCH | |
| Fabricantes | Seiko | |
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S-57M1 Series
www.sii-ic.com
© SII Semiconductor Corporation, 2011-2013
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.1.2_01
The S-57M1 Series, developed by CMOS technology, is a high-accuracy Hall IC that operates with a high-sensitivity, a
high-speed detection and low current consumption.
The output voltage changes when the S-57M1 Series detects the intensity level of magnetic flux density and a polarity
change. Using the S-57M1 Series with a magnet makes it possible to detect the rotation status in various devices.
High-density mounting is possible by using the small SOT-23-3 package.
Due to its high-accuracy magnetic characteristics, the S-57M1 Series can make operation’s dispersion in the system
combined with magnet smaller.
Caution
This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or
automobile equipment including car audio, keyless entry and engine control unit, contact to
SII Semiconductor Corporation is indispensable.
Features
• Pole detection:
• Detection logic for magnetism*1:
• Output form*1:
• Magnetic sensitivity:
• Operation cycle (current consumption):
• Power supply voltage range:
• Operation temperature range:
• Lead-free (Sn 100%), halogen-free*2
Bipolar latch
VOUT = "L" at S pole detection
VOUT = "H" at S pole detection
Nch open-drain output, CMOS output
BOP = 3.0 mT typ.
tCYCLE = 50 μs (1400 μA) typ.
VDD = 2.7 V to 5.5 V
Ta = −40°C to +125°C
*1. The option can be selected.
*2. Refer to " Product Name Structure" for details.
Applications
• Motor
• Housing equipment
• Industrial equipment
Package
• SOT-23-3
1
1 page  
Rev.1.2_01
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-57M1 Series
Electrical Characteristics
Table 5
Item Symbol
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Condition
Min.
Typ. Max.
Unit
Test
Circuit
Power supply voltage VDD
Current consumption IDD
Output voltage
VOUT
Leakage current
ILEAK
−
Average value
Nch open-drain output Output transistor Nch,
product
IOUT = 2 mA
Output transistor Nch,
CMOS output product
IOUT = 2 mA
Output transistor Pch,
IOUT = −2 mA
Nch open-drain output product
Output transistor Nch, VOUT = 5.5 V
2.7 5.0 5.5
− 1400 2000
− − 0.4
−
VDD −
0.4
−
−
−
−
0.4
−
1
V
μA
V
V
V
μA
−
1
2
2
3
4
Operation cycle
tCYCLE
−
− 50 100 μs −
Magnetic Characteristics
Table 6
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item
Symbol
Condition
Min. Typ. Max. Unit Test Circuit
Operation point*1 S pole
BOP
−
1.4 3.0 4.0 mT
5
Release point*2
N pole
BRP
−
−4.0 −3.0 −1.4 mT
5
Hysteresis width*3
BHYS
BHYS = BOP − BRP
−
6.0
− mT
5
*1. BOP: Operation point
BOP is the value of magnetic flux density when the output voltage (VOUT) changes after the magnetic flux density applied
to the S-57M1 Series by the magnet (S pole) is increased (by moving the magnet closer).
VOUT retains the status until a magnetic flux density of the N pole higher than BRP is applied.
*2. BRP: Release point
BRP is the value of magnetic flux density when the output voltage (VOUT) changes after the magnetic flux density applied
to the S-57M1 Series by the magnet (N pole) is increased (by moving the magnet closer).
VOUT retains the status until a magnetic flux density of the S pole higher than BOP is applied.
*3. BHYS: Hysteresis width
BHYS is the difference of magnetic flux density between BOP and BRP.
Remark The unit of magnetic density mT can be converted by using the formula 1 mT = 10 Gauss.
5
5 Page 
Rev.1.2_01
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-57M1 Series
Precautions
• If the impedance of the power supply is high, the IC may malfunction due to a supply voltage drop caused by feed-
through current. Take care with the pattern wiring to ensure that the impedance of the power supply is low.
• Note that the IC may malfunction if the power supply voltage rapidly changes.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• Large stress on this IC may affect on the magnetic characteristics. Avoid large stress which is caused by bend and
distortion during mounting the IC on a board or handle after mounting.
• SII Semiconductor Corporation claims no responsibility for any disputes arising out of or in connection with any
infringement by products including this IC of patents owned by a third party.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet S-57M1.PDF ] | |
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