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Número de pieza | S-25C512A | |
Descripción | SPI SERIAL E2PROM | |
Fabricantes | Seiko | |
Logotipo | ||
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No Preview Available ! S-25C512A
www.sii-ic.com
© SII Semiconductor Corporation, 2010-2015
SPI SERIAL E2PROM
Rev.2.2_02_S
The S-25C512A is a SPI serial E2PROM which operates at high speed, with low current consumption and the wide range
operation. The S-25C512A has the capacity of 512 K-bit and the organization of 65536 words × 8-bit. Page write and
sequential read are available.
Features
• Operating voltage range:
Read 1.6 V to 5.5 V
Write 1.7 V to 5.5 V
• Operation frequency:
• Write time:
• SPI mode (0, 0) and (1, 1)
• Page write:
• Sequential read
• Write protect:
Protect area:
10.0 MHz (VCC = 2.5 V to 5.5 V)
5.0 ms max.
128 bytes / page
Software, Hardware
25%, 50%, 100%
• Monitors write to the memory by a status register
• Function to prevent malfunction by monitoring clock pulse
• Write protect function during the low power supply voltage
• CMOS schmitt input ( CS , SCK, SI, WP , HOLD )
• Endurance:
• Data retention:
• Memory capacity:
• Initial delivery state:
• Operation temperature range:
• Lead-free (Sn 100%), halogen-free*2
106cycles / unit*1 (Ta = +25°C)
100 years (Ta = +25°C)
512 K-bit
FFh, SRWD = 0, BP1 = 0, BP0 = 0
Ta = −40°C to +85°C
*1. For each unit (unit: the 4 bytes with the same address of A15 to A2)
*2. Refer to “ Product Name Structure” for details.
Packages
• 8-Pin SOP (JEDEC)
• 8-Pin TSSOP
Caution This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or
automobile equipment including car audio, keyless entry and engine control unit, contact to SII
Semiconductor Corporation is indispensable.
1
1 page Rev.2.2_02_S
SPI SERIAL E2PROM
S-25C512A
DC Electrical Characteristics
Item
Current consumption (READ)
Symbol Condition
ICC1
No load at
SO pin
Table 8
Ta = −40°C to +85°C
VCC = 1.6 V to 1.8 V VCC = 1.8 V to 2.5 V VCC = 2.5 V to 5.5 V
fSCK = 2.0 MHz
fSCK = 5.0 MHz
fSCK = 10.0 MHz
Min. Max. Min. Max. Min. Max.
− 2.5 − 2.5 − 4.0
Unit
mA
Item
Current consumption (WRITE)
Symbol Condition
ICC2
No load at
SO pin
Table 9
Ta = −40°C to +85°C
VCC = 1.7 V to 1.8 V VCC = 1.8 V to 2.5 V VCC = 2.5 V to 5.5 V
fSCK = 2.0 MHz
fSCK = 5.0 MHz
fSCK = 10.0 MHz
Min. Max. Min. Max. Min. Max.
− 4.0 − 4.0 − 4.0
Unit
mA
Item
Symbol
Condition
Table 10
Ta = −40°C to +85°C
VCC = 1.6 V to 1.8 V VCC = 1.8 V to 2.5 V VCC = 2.5 V to 5.5 V
Min. Max. Min. Max. Min. Max.
Unit
Standby current
consumption
ISB
Input leakage current
Output leakage current
Low level
output voltage
High level
output voltage
ILI
ILO
VOL1
VOL2
VOH1
VOH2
CS = VCC,
SO = Open
Other inputs are
− 3.0 − 4.0 − 8.0
VCC or GND
VIN = GND to VCC
−
1.0
−
1.0
−
1.0
VOUT = GND to VCC
−
1.0
−
1.0
−
1.0
IOL = 2.0 mA
− − − 0.4 − 0.4
IOL = 1.5 mA
− 0.4 − 0.4 − 0.4
IOH = −2.0 mA
− − 0.8 × VCC − 0.8 × VCC −
IOH = −0.4 mA
0.8 × VCC − 0.8 × VCC − 0.8 × VCC −
μA
μA
μA
V
V
V
V
5
5 Page Rev.2.2_02_S
SPI SERIAL E2PROM
S-25C512A
Operation
1. Status register
The status register’s organization is below. The status register can Write and Read by a specific instruction.
b7 b6 b5 b4 b3 b2 b1 b0
SRWD
0
0
0 BP1 BP0 WEL WIP
Status Register Write Disable
Block Protect
Write Enable Latch
Write In Progress
Figure 9 Organization of Status Register
The status / control bits of the status register as follows.
1. 1 SRWD (b7) : Status Register Write Disable
Bit SRWD operates in conjunction with the Write protect signal ( WP ). With a combination of bit SRWD and signal
WP (SRWD = “1”, WP = “L”), this device goes in Hardware Protect status. In this case, the bits composed of the
nonvolatile bit in the status register (SRWD, BP1, BP0) go in Read Only, so that the WRSR instruction is not be
performed.
1. 2 BP1, BP0 (b3, b2) : Block Protect
Bit BP1 and BP0 are composed of the nonvolatile memory. The area size of Software Protect against WRITE
instruction is defined by them. Rewriting these bits is possible by the WRSR instruction. To protect the memory area
against the WRITE instruction, set either or both of bit BP1 and BP0 to “1”. Rewriting bit BP1 and BP0 is possible
unless they are in Hardware Protect mode. Refer to “ Protect Operation” for details of “Block Protect”.
1. 3 WEL (b1) : Write Enable Latch
Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is
“1”, this is the status that Write Enable Latch is set. If bit WEL is “0”, Write Enable Latch is in reset, so that the
device does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;
• The power supply voltage is dropping
• Power-on
• After performing WRDI
• After the Write operation by the WRSR instruction has completed
• After the Write operation by the WRITE instruction has completed
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet S-25C512A.PDF ] |
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