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Número de pieza | CN8236 | |
Descripción | ATM ServiceSAR Plus | |
Fabricantes | Mindspeed | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CN8236 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! CN8236
ATM ServiceSAR Plus with xBR Traffic Management
The CN8236 Service Segmentation and Reassembly Controller integrates ATM terminal
functions, PCI Bus Master and Slave controllers, and a UTOPIA level 1 or 2 interface
with service-specific functions in a single package for AAL0, 3/4, and 5 operations.
The ServiceSAR Controller generates and terminates ATM traffic and automatically
schedules cells for transmission. The CN8236 is targeted at 155 Mbps throughput
systems where the number of VCCs is relatively large, or the performance of the overall
system is critical. Examples of such networking equipment include Routers, Ethernet
switches, ATM Edge switches, or Frame Relay switches.
Service-Specific Performance Accelerators
The CN8236 incorporates numerous service-specific features designed to accelerate
and enhance system performance. As examples, the CN8236 implements Echo
Suppression of LAN traffic via LECID filtering, and supports Frame Relay DE to CLP
interworking.
Advanced xBR Traffic Management
The xBR Traffic Manager in the CN8236 supports multiple ATM service categories. This
includes CBR, VBR (both single and dual leaky bucket), UBR, GFR (Guaranteed Frame
Rate), and ABR. The CN8236 manages each VCC independently. It dynamically
schedules segmentation traffic to comply with up to 16+CBR user-configured
scheduling priorities for the various traffic classes. Scheduling is controlled by a
Schedule table configured by the user and based on a user-specified time reference.
ABR channels are managed in hardware according to user-programmable ABR
templates. These templates tune the performance of the CN8236’s ABR algorithms to a
specific system’s or network’s requirements.
–Continued–
Distinguishing Features
Service-Specific Performance
Accelerators
• LECID filtering and echo suppression
• Dual leaky bucket based on CLP
(frame relay)
• Frame relay DE interworking
• Internal SNMP MIB counters
• IP over ATM; supports both CLP0+1
and ABR shaping
Flexible Architectures
• Multi-peer host
• Direct switch attachment via reverse
UTOPIA
• ATM terminal
– Host control
– Local bus control
• Optional local processor
–Continued–
Functional Block Diagram
Timer
Counters
Multi-client
PCI Bus
PCI DMA
Master/ Co-
Slave Proc'r
Local Bus
Local Memory
Interface
Control/
Status
Reassembly
Coprocessor
Segmentation
Coprocessor
Cell
FIFO
UTOPIA
Master/Slave
Rx/Tx
CBR, VBR, ABR,
UBR, GFR
CN8236
Traffic Manager
Patent Pending
CN8250
PHY
Device
Data Sheet
28236-DSH-001-B
May 2003
1 page –Continued Distinguishing Features–
Generous Implementation of OAM-PM
Protocols
• Detection of all F4/F5 OAM flows
• Internal PM monitoring and
generation for up to 128 VCCs
• Optional global OAM Rx/Tx queues
• In-line OAM insertion and generation
Standards-Based I/O
• 33 MHz PCI 2.1 (to 40 MHz)
• Serial EEPROM to store PCI
configuration information
• PHY interfaces
– UTOPIA master (Level 1)
– UTOPIA slave (Level 1)
– UTOPIA master (Level 2)
– UTOPIA slave (Level 2)
• Flexible SAR-shared memory
architecture
• Optional local control interface
• Boundary scan for board-level testing
• Source loopback, for diagnostics
• Glueless connection to Mindspeed’s
ATM physical layer device, the
RS825x and Bt8223
Standards Compliance
• UNI/NNI 3.1
• TM 4.0/TM4.1
• Bellcore GR-1248
• ATM Forum B-ICI V2.0
28236-DSH-001-B
Mindspeed Technologies™
5 Page CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Table of Contents
5.5 Global Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.6 Status Queue Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
5.6.1 Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
5.6.1.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
5.6.1.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
5.6.1.3 Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
5.6.1.4 Host Detection of Status Queue Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
5.6.2 Status Queue Overflow or Full Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
5.7 Reassembly Control and Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
5.7.1 Channel Lookup Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
5.7.2 Reassembly VCC Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
5.7.2.1 AAL5, AAL0 and AAL3/4 VCC Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
5.7.2.2 AAL3/4 Head VCC Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
5.7.3 Reassembly Buffer Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
5.7.4 Free Buffer Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
5.7.5 Reassembly Status Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51
5.7.6 LECID Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
5.7.7 Global Time-Out Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56
5.7.8 Reassembly Internal SRAM Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
6.0 Traffic Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.1 xBR Cell Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.1.2 ABR Flow Control Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.2 xBR Cell Scheduler Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.2.1 Scheduling Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.2.1.1 16 Priority Levels + CBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.2.1.2 VCC Priority Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.2.2 Dynamic Schedule Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.2.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.2.2.2 Schedule Table Slots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.2.2.3 Schedule Slot Formats without USE_SCH_CTRL Asserted . . . . . . . . . . . . . . . . 6-10
6.2.2.4 Schedule Slot Formats with USE_SCH_CTRL Asserted . . . . . . . . . . . . . . . . . . 6-12
6.2.2.5 Some Scheduling Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.2.3 CBR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.2.3.1 CBR Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.2.3.2 Available Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.2.3.3 CBR Cell Delay Variation (CDV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.2.3.4 CBR Channel Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.2.4 VBR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.2.4.1 Mapping CN8236 VBR Service Categories to TM 4.1 VBR Service Categories . . 6-19
6.2.4.2 Rate-Shaping vs. Policing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.2.4.3 Single Leaky Bucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
28236-DSH-001-B
Mindspeed Technologies™
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet CN8236.PDF ] |
Número de pieza | Descripción | Fabricantes |
CN8236 | ATM ServiceSAR Plus | Mindspeed |
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