PDF K4N26323AE-GC Data sheet ( Hoja de datos )

Número de pieza	K4N26323AE-GC
Descripción	128Mbit GDDR2 SDRAM
Fabricantes	Samsung
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No Preview Available ! K4N26323AE-GC 128M GDDR2 SDRAM 128Mbit GDDR2 SDRAM 1M x 32Bit x 4 Banks GDDR2 SDRAM with Differential Data Strobe and DLL Revision 1.7 January 2003 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.7 (Jan. 2003) 1 page K4N26323AE-GC PIN CONFIGURATION Normal Package (Top View) 128M GDDR2 SDRAM 234 B DQS0 /DQS0 VSSQ 5 DQ3 6 DQ2 7 DQ0 8 DQ31 9 DQ29 10 DQ28 11 12 13 VSSQ /DQS3 DQS3 C DQ4 DM0 VDDQ VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ VDDQ DM3 DQ27 D DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25 E DQ7 F DQ17 G DQ19 H DQS2 J DQ20 K DQ21 VDDQ DQ16 DQ18 /DQS2 DM2 DQ22 VDD VDDQ VDDQ NC VDDQ VDDQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSS VSS NC, VSS NC, VSS NC, VSS NC, VSS VSS VSS NC, VSS NC, VSS NC, VSS NC, VSS VSS VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDDQ DQ15 DQ13 /DQS1 DM1 DQ9 DQ24 DQ14 DQ12 DQS1 DQ11 DQ10 L DQ23 M VREF A3 A2 VDD A10 VSS /RAS RFU2 NC VDD CKE VDD NC RFU1 ZQ VSS /CS VDD A9 A4 DQ8 A5 VREF N A0 A1 A11 BA0 /CAS CK /CK /WE BA1 A8/AP A6 A7 NOTE : 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. (M,13) VREF for CMD and ADDRESS 4. (M,2) VREF for Data input -5- Rev. 1.7 (Jan. 2003) 5 Page K4N26323AE-GC 128M GDDR2 SDRAM MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of GDDR2 SDRAM. It programs CAS latency, addressing mode, test mode and various vendor specific options to make GDDR2 SDRAM useful for variety of dif- ferent applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR2 SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum four clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is used for test mode. A9 ~ A11 are used for tWR. Refer to the table for specific codes for various addressing modes and CAS latencies. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 00 tWR 0 TM CAS Latency BT Burst Length Mode Register * Test Mode Burst Length 1 A7 mode A2 A1 A0 Burst Length BA0 An ~ A0 0 Normal 010 4 0 MRS 1 Test Burst Type 1 EMRS 0 A3 Burst Type 0 Sequential tWR A11 A10 A9 000 001 010 011 100 101 110 111 MRS Select Reserved Reserved 3 4 5 Reserved Reserved Reserved CAS Latency A6 A5 A4 000 001 010 011 100 101 110 111 Latency Reserved Reserved Reserved Reserved Reserved 5 6 7 1. BL 4, Sequential Only - 11 - Rev. 1.7 (Jan. 2003) 11 Page

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