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PDF 8V97053L Data sheet ( Hoja de datos )
| Número de pieza | 8V97053L | |
| Descripción | Low Power Wideband Fractional RF Synthesizer / PLL | |
| Fabricantes | IDT | |
| Logotipo |  |
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Low Power Wideband Fractional
RF Synthesizer / PLL
8V97053L
Datasheet
General Description
The 8V97053L is a high performance Wideband RF Synthesizer /
PLL optimized for use as the local oscillator (LO) in Multi-Carrier,
Multi-mode FDD & TDD Base Station radio card. It is offered in a
compact 5x5, 32-VFQFN package.
The 8V97053L Wideband RF Synthesizer / PLL offers a default
Fractional Mode with the option to use it with an Integer mode. It
requires an external loop filter.
The 8V97053L with integrated Voltage Controlled Oscillator (VCO)
supports output frequencies from 34.375MHz to 4400MHz and
maintains superior phase noise and spurious performance.
RF_OUT[A:B] output drivers have independently programmable
output power ranging from –4dBm to +7dBm. The RF_OUT outputs
can be muted. The mute function is accessible via a SPI command
or mute pin.
The operation of the 8V97053L is controlled by writing to registers
through a 3-wire SPI interface. The 8V97053L also has an additional
option that allows users to read back values from registers by
configuring the MUX_OUT pin as a SDO for the SPI interface. The
SPI interface is compatible with 1.8V logic and tolerant to 3.3V.
In multi-service base stations, very low noise oscillators are required
to generate a large variety of frequencies to the mixers while
maintaining excellent phase noise performance and low power. The
8V97053L offers a large tuning range capable of providing multi-band
local oscillator (LO) frequency synthesis in multi-mode base stations,
thus limiting the use of multiple narrow band RF Synthesizers and
reducing the BOM complexity and cost. The device can operate over
-40°C to +85°C industrial temperature range.
Applications
• Wireless Infrastructure
• Test Equipment
• CATV Equipment
• Military and Aerospace
• Wireless LAN
• Clock Generation
Features
• Dual Differential Outputs
• Output frequency range: 34.375MHz to 4400MHz (continuous
range)
• RF Output Divide by 1, 2, 4, 8, 16, 32, 64
• Open Drain Outputs (see Output Distribution Section)
• Fractional-N synthesizer (also supports Integer-N mode)
• 16-bit integer and 12-bit fractional
(16-bit fractional when using the extended registers)
• 3- or 4-wire SPI interface (compatible with 3.3V and 1.8V)
• Single 3.3V supply
• Logic compatibility: 1.8V
• Integrated high performance low dropout regulators (LDOs) for
excellent power supply noise rejection
• Programmable output power level: -4dBm to +5dBm
(up to +7 when using the extended registers)
• Mute Function
• Ultra low PN for 1.65GHz LO: -142.21dBc/Hz @ 1MHz Offset,
(typical)
• Lock Detect Indicators
• Input Reference frequency: 5MHz to 310MHz
• 32-Lead, 5x5 VFQFN package
• Automatic VCO band selection (Autocal feature)
• -40°C to +85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
• Supports case temperature 105°C operations
©2016 Integrated Device Technology, Inc.
1
August 18, 2016
1 page  
8V97053L Datasheet
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 15A. AC Characteristics, VDDX = VDDA = 3.3V ± 5%, TA = -40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 15B. RF_OUT[A:B] Phase Noise and Jitter Characteristics, VDDX = VDDA = 3.3V ± 5%, TA = -40°C to 85°C . . . . . . . . . . . . . . . . .48
Phase Noise (Closed-Loop) at 156.25MHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Phase Noise (Closed-Loop) at 1.76GHz (3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Phase Noise (Closed-Loop) at 2.05GHz (3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Phase Noise (Open-Loop) at 745MHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Phase Noise Performance (Open-Loop) at 1.1GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Phase Noise Performance (Open-Loop) at 1.65GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Phase Noise Performance (Open-Loop) at 2.3GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Phase Noise Performance (Open-Loop) at 3.8GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Phase Noise Performance (Open-Loop) at 4.4GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Loop Filter Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2nd Order Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 11. Typical 2nd Order Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3rd Order Loop Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 12. Typical 3rd Order Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Recommendations for Unused Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Schematic Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 13A. An 8V97053L General Application Schematic Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 13B. Schematic Example for Driving Single Ended Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 16. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Example 2: VCO Frequency Range = 2590MHz to 3624MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Reliability Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 17A. JA vs. Air Flow Table for a 32 lead VFQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 17B. JB vs. Air Flow Table for a 32 lead VFQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
32-Lead VFQFN Package Outline and Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
32-Lead VFQFN Package Outline and Package Dimensions (Continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 18. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 19. Pin 1 Orientation in Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
©2016 Integrated Device Technology, Inc.
5
August 18, 2016
5 Page 
8V97053L Datasheet
Feedback Divider
The feedback divider N supports fractional division capability in the PLL feedback path. It consists in an integer N divider of 16-bits, and a
Fractional divider of 12-bits (FRAC) over 12-bits (MOD). FRAC and MOD can be extended to 16-bits when using extended registers.
To select an integer mode only, the user sets FRAC to 0.
FROM VCO OUTPOUT
or FROM M0 OUTPUT
N counter
TO PFD
3rd Order
ΣΔ Modulator
12 Bit FRAC
+16 Bit INT
12 Bit MOD
Figure 1. RF Feedback N Divider
The 16 INT bits (Bit[D30:D15] in Register 0) set the integer part of the feedback division ratio.
The 12 FRAC bits (Bit[D14:D3] in Register 0) set the numerator of the fraction that goes into the Sigma Delta modulator. FRAC can be extended
to 16-bits using the EXT_FRAC bits in Register 7.
The 12 MOD bits (Bit[D14:D3] in Register 1) set the denominator of the fraction that goes into the Sigma Delta modulator. MOD can be
extended to 16-bits using the EXT_MOD bits in Register 7.
From the relation (2), the VCO minimum step frequency is determined by (1/MOD) * fPFD.
FRAC values from 0 to (MOD – 1) cover channels over a frequency range equal to the PFD reference frequency.
The PFD frequency is calculated as follows:
(3)
Use 2R instead of R if the Reference Divide by 2 is used.
REFCLK = the input reference frequency (REF_IN)
D = the input reference doubler (0 if not active or 1 if active)
R = the 10-Bits programmable input reference pre-divider
The programmable modulus (MOD) is determined based on the input reference frequency (REF_IN) and the desired channelization (or output
frequency resolution). The high resolution provided on the R counter and the Modulus allows the user to choose from several configuration (by
using the doubler or not) of the PLL to achieve the same channelization. Using the doubler may offer better phase noise performance. The
high resolution Modulus also allows to use the same input reference frequency to achieve different channelization requirements. Using a
unique PFD frequency for several needed channelization requirements allows the user to design a loop filter for the different needed setups
and ensure the stability of the loop.
The channelization is given by
(4)
In low noise mode (dither disabled), the Sigma Delta modulator can generate some fractional spurs that are due to the quantization noise.
©2016 Integrated Device Technology, Inc.
11
August 18, 2016
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 8V97053L.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 8V97053 | Low Power Wideband Fractional RF Synthesizer / PLL | IDT |
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